Re-targeting the design to the Production Board

Frozen Content

Once the design has been captured, the first thing you will want to do is to see if it can be synthesized and if a place and route can be performed.

What is required to target a design to your board?

The design captured in the source documents (schematic/OpenBus/HDL) defines the behavior of the circuit. To map this design into an FPGA which is part of a larger PCB design, requires the addition of all the necessary implementation information. This information could include:

  • The target PCB project
  • The target FPGA
  • FPGA net-to-physical devicepin assignments
  • Pin configuration information, such as output voltage settings
  • Design timing constraints, such as allocating a specific net to a special function FPGA pin
  • FPGA place and route constraints.

How the nets in the design connect to the FPGA pins

Any net that you want connected to a physical pin on the FPGA must be wired to a port on the top schematic sheet. When the design is compiled, the top sheet is scanned and all nets that connect to ports are assumed to connect to physical pins on the FPGA.

In the FPGA design domain, these connection points are also referred to as ports. While the ports are defined on the schematic, the pins they are assigned to are defined in a constraint file.

As well as placing a port to identify a net (or bus) as connecting to a physical pin (or set of pins), you can also use a component, as long as it includes the parameter PortComponent = True. When the design is synthesized, each pin in the Port Componentis converted to a port, with the port named the same as the pin designator.

How the implementation information is included

The implementation information is stored in constraint files. A constraint file is a set of constraint records, where each record (or constraint group) defines one or more constraints to be applied to a target in the FPGA project. The constraint file system supports storing all this information in one constraint file, or splitting it into multiple files.

The minimum constraint information required to move to synthesis is the device specification.

Like source documents, constraint files are added to the project. They are then mapped to the FPGA project by creating a suitable Configuration, where the configuration is a set of constraints that map the FPGA design to a target implementation (the actual device on a PCB).

Creating a Constraint File and Specifying the Device
Assigning Nets to FPGA Pins in the Constraint File
Creating a Configuration
Design Synthesis
Vendor Place and Route Software
Importing Vendor-generated Pin Constraints
Converting Parts to Ports

See Also

Design Portability, Configurations and Constraints
Constraint File Reference

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