Assigning Nets to FPGA Pins in the Constraint File

Frozen Content

The net (or port)-to-physical pin assignments also need to be defined in a constraint file. You can manually define the assignments, or let the place and route tools assign them and then import the assignments back into the constraint file.

Typically there will be certain ports that you will want to assign, such as clock nets, then let the place and route process assign the rest. Once the FPGA is placed on the PCB, pin assignments can be changed to optimize the PCB routing and the changes back-annotated to the FPGA project.

  1. To add port assignments to the constraint file, select Design » Import Port Constraints from Project from the constraint file editor menus. A constraint record will be added for each port in the FPGA project. At this stage there will be no actual pins assigned to the ports.
     
  2. To manually assign a port to an FPGA pin, you add the FPGA_PINNUM constraint to the record. For example, to assign CLK_REF to pin 185 in a Xilinx device, the constraint would look like:
     
    Record=Constraint | TargetKind=Port | TargetId=CLK_REF | FPGA_PINNUM=P185
     
    Note: For QFP-packaged FPGAs, valid pin numbers may begin with the letter P, immediately followed by the pin number. For example, P22 means pin 22. For FPGAs in PGA or BGA packages, the pin number is a grid reference. For example, A22 is the pin on Row A, Column 22, and P22 is Row P, Column 22.
     
  3. For a clock you may prefer to instruct the place and route tools which ports are to be assigned to clock pins, then let the place and route tool choose from the available clock pins on the target device. To constrain the CLK_REF port to an FPGA clock resource, the constraint would look like:
     
    Record=Constraint | TargetKind=Port | TargetId=CLK_REF | FPGA_CLOCK=TRUE
     

    Figure 1. Sample constraint file, with two clock nets constrained by the FPGA_CLOCK=TRUE constraint.
    Note that the pin allocations have not been defined yet.

When the place and route process is complete, the pin assignments can be imported into the constraint file.

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