Design Synthesis

Frozen Content

Synthesis is the process of translating the schematic and behavioural VHDL descriptions of the design into a low-level form suitable for the vendor place and route tools. The synthesis engine first creates an intermediate VHDL description of the design, and then synthesizes this into EDIF.

Synthesis can be launched in a number of ways:

  • right-click on the project file in the Projects panel and select Synthesis from the menu that appears
  • open the Devices view and click the Synthesize button in the Process Flow associated to the targeted physical device.

Note that whenever a synthesis is performed, a suitable configuration must be available. If there are multiple configurations to choose from, a selection dialog will appear. In the Devices view, the project and configuration combination are selected in the drop down list.

During synthesis, use the Messages panel to monitor the progress and double-click to explore any errors that occur.

Related Topics

For information on using the Devices view to process the design, see Processing the Captured FPGA Design.

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