WB_I2S - Configurable Wishbone Audio Streaming Controller

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Figure 1. WB_I2S - Configurable Wishbone Audio Streaming Controller.

The Configurable Audio Streaming Controller component (WB_I2S) is used to facilitate data transfers over the inter-IC sound (I2S) bus. The I2S bus – developed by Philips as a dedicated serial link for digital audio – allows a standardized communication medium for an ever-increasing array of digital audio devices.

The standard I2S bus consists of three lines:

  • a data line, consisting of two time-division-multiplexed channels (Left and Right). Note: The WB_I2S Controller uses two data lines – one to transmit data and one to receive data
  • a word select line
  • a clock line.

The WB_I2S acts as a Master on the bus and, as such, generates the continuous serial bit clock and the word select signal for the bus.

For further information on the I2S bus, refer to the I2S bus specification.

The WB_I2S is an enhanced version of the legacy I2S_W peripheral. As part of its configurable nature, it allows you to enable, and define, a much larger hardware buffer than its standard built-in 32 x 24-bit buffer. With larger FIFO buffers, interrupts can be disabled and simple periodic polling of the state of the Transmit and Receive buffers performed instead. Additional internal registers are used to store the values for the pointers to the Head and Tail of each buffer, enabling you to ascertain how many samples are currently available to be read in the Receive Buffer, and how much sample space is available for writing new samples in the Transmit Buffer.
Like the I2S_W, the WB_I2S provides for transmission and reception of data. Unlike the I2S_W however, you can configure the WB_I2S to just transmit data or just receive data.
Should you wish to configure the WB_I2S to functionally behave in the same fashion as the I2S_W – essentially using it in what can be termed 'Legacy Mode' – simply enable the device for transmission and reception of data, and disable the hardware buffer option. For more information, see Configuration.

Features at-a-glance

  • I2S-compatible interface
  • Operates as I2S Master
  • Configurable from the OpenBus System document or Schematic sheet
  • Operational as Transmitter and/or Receiver
  • Supports four data word widths:
    • 16, 20, 24 and 32 bit word widths
  • Three modes of I2S communication supported:
    • Normal (non-justified)
    • Left-justified
    • Right-justified
  • Ability to include/exclude larger hardware buffer for Transmitter/Receiver
    • Included: Choose buffer size from 1K/2K/4K/8K x 24-bit word
    • Excluded: Standard (built-in) 32 x 24-bit word buffer used
  • Independently selectable mono/stereo for Receiver and Transmitter
  • Wishbone-compliant
  • Wishbone data to Transmitter right-aligned in 16, 20 and 24 bit word-width modes (bit 0 is the LSB)
  • Wishbone data to Transmitter left-aligned in 32 bit word-width mode (bit 31 is the MSB)


From an OpenBus System document, the Configurable Audio Streaming Controller component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the WB_I2S component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the WB_I2S

Use the following links to explore use of the WB_I2S in more detail:

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