WB_I2S - Accessible Internal Registers

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Modified by Admin on Sep 13, 2017

Control Register (CONTROL)
Mode Register (MODE)
Status Register (STATUS)
Data Register (DATA)
Receiver FIFO Pointers Register (RX_POINTERS)
Transmitter FIFO Pointers Register (TX_POINTERS)

The following sections detail the internal registers for the WB_I2S Controller that can be accessed from the host processor.

Control Register (CONTROL)

Address: 0h

Access: Read and Write

Value after Reset: 0000_0000h

This register is used to store the prescaler and watermark values for the Controller.

Table 1. The CONTROL register.

MSB LSB
31 16	15	14 8	7 0
watermark	cpen	-	prescaler

Table 2. The CONTROL register bit functions.

Bit	Symbol	Function
CONTROL.31..CONTROL.16	watermark	Watermark value, effectively used to set the interrupt generation point for both the Transmitter and Receiver.
CONTROL.15	cpen	Clock Prescaler Enable. Set this bit to '1' to enable use of the prescaler value.
CONTROL.14..CONTROL.8	-	Not Used. These bits will be ignored when writing to the register and will return '0' when reading it.
CONTROL.7..CONTROL.0	prescaler	Prescaler value, used to divide the CLK_I signal frequency to 256*sample frequency.

Mode Register (MODE)

Address: 1h

Access: Read and Write

Value after Reset: 0000_0018h

This register is used to set the operational mode of the Controller and to enable interrupts for the Transmitter and Receiver respectively.

Table 3. The MODE register.

MSB LSB
31 17	16 15	14	13	12	11	10	9	8	7	6	5 0
-	wjust	rxie	txie	rxen	txen	slr	mi	mo	-	-	wwidth

Table 4. The MODE register bit functions.

Bit	Symbol	Function
MODE.31..MODE.17	-	Not Used. These bits will be ignored when writing to the register and will return '0' when reading it.
MODE.16..MODE.15	wjust	Word Justification. 00 = Normal 01 = Left Justified 10 = Right Justified
MODE.14	rxie	Receiver Interrupt Enable. 0 = Disabled 1 = Enabled
MODE.13	txie	Transmitter Interrupt Enable. 0 = Disabled 1 = Enabled
MODE.12	rxen	Receiver Enable. 0 = Disabled 1 = Enabled
MODE.11	txen	Transmitter Enable. 0 = Disabled 1 = Enabled
MODE.10	slr	Select Left/Right for Mono In. 0 = Left 1 = Right This bit is ignored if the `mi` bit (MODE.9) = 0.
MODE.9	mi	Mono In. 0 = Stereo 1 = Mono
MODE.8	mo	Mono Out. 0 = Stereo 1 = Mono
MODE.7..MODE.6	-	Not Used. These bits will be ignored when writing to the register and will return '0' when reading it.
MODE.5..MODE0	wwidth	Word Width. Valid values are: 16 (010000) 20 (010100) 24 (011000) 32 (100000)

Status Register (STATUS)

Address: 2h

Access: Read only

Value after Reset: 0000_0032h

This register is used to determine the current state of the Controller.

Table 5. The STATUS register.

MSB LSB
31 16	15 8	7	6	5	4	3	2	1	0
coresize	corerev	rxw	rxf	rxe	rxlr	txw	txf	txe	txlr

Table 6. The STATUS register bit functions.

Bit	Symbol	Function
STATUS.31..STATUS.16	coresize	Core Size. This is the 16-bit binary representation of the width of the FIFO address line. 32 bytes – 0000000000000101 1K bytes – 0000000000001010 2K bytes – 0000000000001011 4K bytes – 0000000000001100 8K bytes – 0000000000001101
STATUS.15..STATUS.8	corerev	Core Revision. The revision of the WB_I2S peripheral. This is constant and defined as "00000001".
STATUS.7	rxw	Receive FIFO Watermark state. 0 = Watermark not reached 1 = Watermark reached
STATUS.6	rxf	Receive FIFO Full state. 0 = Not Full 1 = Full
STATUS.5	rxe	Receive FIFO Empty state. 0 = Not Empty 1 = Empty
STATUS.4	rxlr	Receive FIFO Left/Right state. 0 = Next data is from Left channel 1 = Next data is from Right channel
STATUS.3	txw	Transmit FIFO Watermark state. 0 = Watermark not reached 1 = Watermark reached
STATUS.2	txf	Transmit FIFO Full state. 0 = Not Full 1 = Full
STATUS.1	txe	Transmit FIFO Empty state. 0 = Not Empty 1 = Empty
STATUS.0	txlr	Transmit FIFO Left/Right state. 0 = Next data is for Left channel 1 = Next data is for Right channel

Data Register (DATA)

Address: 3h

Access: Read and Write

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Buffers. Performing a Wishbone Write (WE_I input High) to the DATA address loads data directly into the Transmit Buffer.

Performing a Wishbone Read (WE_I input Low) from the DATA address retrieves data directly from the Receive Buffer. If no data words are available in the Receive Buffer, the returned data is invalid. Otherwise, the retrieved data word is removed from the buffer, effectively freeing up space.

Receiver FIFO Pointers Register (RX_POINTERS)

Address: 4h

Access: Read only

Value after Reset: 1K Buffer (03FF_0000h), 2K Buffer (07FF_0000h), 4K Buffer (0FFF_0000h), 8K Buffer (1FFF_0000h)

This register is used to contain the current positions for the head and tail of the Receive buffer. These positions are reflected by the values of two associated pointers.

This register is only available if the WB_I2S has been configured to use a larger hardware buffer. The values for the head and tail, read back from this register, are used to calculate the number of samples that are available in the Receive buffer. The processor in the design can essentially poll this register, rather than having the WB_I2S set-up to be interrupt-driven.

Table 7. The RX_POINTERS register.

MSB LSB
31 16	15 0
rxbuf_tail	rxbuf_head

Table 8. The RX_POINTERS register bit functions.

Bit	Symbol	Function
RX_POINTERS.31..RX_POINTERS.16	rxbuf_tail	Value currently assigned to the pointer that tracks the tail of the Receive buffer.
RX_POINTERS.15..RX_POINTERS.0	rxbuf_head	Value currently assigned to the pointer that tracks the head of the Receive buffer.

Transmitter FIFO Pointers Register (TX_POINTERS)

Address: 5h

Access: Read only

Value after Reset: 1K Buffer (03FF_0000h), 2K Buffer (07FF_0000h), 4K Buffer (0FFF_0000h), 8K Buffer (1FFF_0000h)

This register is used to contain the current positions for the head and tail of the Transmit buffer. These positions are reflected by the values of two associated pointers.

This register is only available if the WB_I2S has been configured to use a larger hardware buffer. The values for the head and tail, read back from this register, are used to calculate the number of samples that can be written to the Transmit buffer. The processor in the design can essentially poll this register, rather than having the WB_I2S set-up to be interrupt-driven.

Table 9. The TX_POINTERS register.

MSB LSB
31 16	15 0
txbuf_tail	txbuf_head

Table 10. The TX_POINTERS register bit functions.

Bit	Symbol	Function
TX_POINTERS.31..TX_POINTERS.16	txbuf_tail	Value currently assigned to the pointer that tracks the tail of the Transmit buffer.
TX_POINTERS.15..TX_POINTERS.0	txbuf_head	Value currently assigned to the pointer that tracks the head of the Transmit buffer.

Content

WB_I2S - Accessible Internal Registers

Contents

Control Register (CONTROL)

Mode Register (MODE)

Status Register (STATUS)

Data Register (DATA)

Receiver FIFO Pointers Register (RX_POINTERS)

Transmitter FIFO Pointers Register (TX_POINTERS)