WB_I2S - Operational Overview

After an external reset, you will need to initialize the WB_I2S Controller. This should be carried out in accordance with design requirements and can include:

• Loading the required values for the watermark and prescaler to the Control register.

• Setting the desired word width using bits 5..0 in the Mode register.

• Setting the desired word justification using bits 16..15 in the Mode register. By default, the Controller will be set to operate in Normal (non-justified) mode.

• Setting the Controller to operate in Mono using bits 10..8 in the Mode register. By default, the Controller will be reset to operate in Stereo mode.

• Enabling Transmitter and/or Receiver interrupts in the Mode register (MODE.13 and MODE.14 respectively).

• Enabling the Transmitter and Receiver by setting bits 11 and 12 in the Mode register respectively. This step should be carried out last in order that the Controller be fully configured to operate as required before data is transmitted and/or received.

Data Transmission

Provided the Transmitter is enabled, the WB_I2S will start sending data as soon as it is available in the Transmit Buffer and the clock signals (SCK, WS) are ready.
 

 
The next data word in the Transmit Buffer is loaded into the Transmit Shift register. Depending on the configured word width, the 16, 20 or 24 bits of data are then shifted out onto the SDO line on each rising edge of SCK – MSB first.

If, when transmitting in Mono (mo bit in Mode register is High), the Transmit Buffer becomes empty, the last sample is repeated until new data is available. This ensures that the target device avoids receiving a "click".

If transmitting in Stereo (mo bit Low) and the Transmit Buffer becomes empty, the "click" is avoided by repeating transmission of the last two samples – Left and Right channels – until new data is available.

Why MSB First?

Serial data is transmitted in two's complement, with the most significant bit sent first. The reason for sending the data MSB first is because the target Receiver may be configured with a different Word Width to the WB_I2S's Transmitter. Sending the MSB first solves the following two scenarios:

• When the target Receiver's Word Width is greater than that of the WB_I2S, the missing bits are simply set to zero, internally, by the Receiver.

• When the target Receiver's Word Width is less than that of the WB_I2S, the bits after the LSB are simply ignored.

Data Reception

Provided the Receiver is enabled, the WB_I2S will start receiving data as soon as the connected remote device sends it.
 

 
The 16, 20 or 24 bits of data sent from the remote device's transmitter are read into the Receive Shift register on each rising edge of SCK. Once all bits in a data word are fully received, it is loaded into the Receive Buffer.

Importance of WS

The WS line not only indicates the channel (Left or Right) being transmitted but is also used to provide effective delimiting between data words. The Transmitter always sends the MSB of the next data word one clock period (of SCK) after WS changes, allowing time for the remote device to:

• Derive synchronize timing for transmission of serial data from its Transmitter section

• Allow the remote device's Receiver to distinguish between the end of one data word and the start of the next.

As the WS signal is generated by the WB_I2S (as Bus Master), the required synchronized timing for the Controller's Receiver section is also derived using this signal, so that the data from the remote device's Transmitter can be received correctly.

One other point to note is that the data channels – Left and Right – are multiplexed, with WS being the selection control. How data is sent depends on whether justification is used.

For normal (non-justified) I2S communication, data is sent in the following fashion:

Right Channel (WS=1) > Left Channel (WS=0) > Right Channel (WS=1) > ...

For left or right justified I2S communication, data is sent in the following fashion:

Right Channel (WS=0) > Left Channel (WS=1) > Right Channel (WS=0) > ...