WB_I2S - Data Transfer Modes

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Modified by Admin on Sep 13, 2017

The following sections detail the available modes of data transfer supported by the WB_I2S Controller. The mode is changed by adjusting the word width, using bits 5..0 of the MODE register.

As a general note, there are some audio devices in the market that do not fully implement the I2S Bus specification. Care should be taken to configure the WB_I2S to only use modes supported by such a device.

16 Bits (Right-Aligned)

For transmission of data, the host processor writes a 32-bit value appearing on the DAT_I bus. The upper 16-bits are ignored. The 24-bit data word loaded into the head of the Transmit Buffer is created as follows:

DAT_I(15..0) & "00000000"

The value sent out on the I2S bus will be:

TX_FIFO(Tail)(15..0)

For reception of data, a 24-bit value will be loaded into the Receive Buffer. Bits 15..0 of this word will be the value received from the I2S bus. The 32-bit value sent back to the host processor on the DAT_O bus will be:

"SSSSSSSSSSSSSSSS" & RX_FIFO(Tail)(15..0),

where S represents the sign bit: RX_FIFO(Tail)(15).

Sign-extending the value read by the host processor in 16-, 20-, or 24-bit modes, allows negative values to remain negative when read as 32-bit values.

20 Bits (Right-Aligned)

For transmission of data, the host processor writes a 32-bit value appearing on the DAT_I bus. The upper 12-bits are ignored. The 24-bit data word loaded into the head of the Transmit Buffer is created as follows:

DAT_I(19..0) & "0000"

The value sent out on the I2S bus will be:

TX_FIFO(Tail)(19..0)

For reception of data, a 24-bit value will be loaded into the Receive Buffer. Bits 19..0 of this word will be the value received from the I2S bus. The 32-bit value sent back to the host processor on the DAT_O bus will be:

"SSSSSSSSSSSS" & RX_FIFO(Tail)(19..0),

where S represents the sign bit: RX_FIFO(Tail)(19).

24 Bits (Right-Aligned)

For transmission of data, the host processor writes a 32-bit value appearing on the DAT_I bus. The upper 8-bits are ignored, with the remaining 24-bit data word (DAT_I(23..0)) loaded into the head of the Transmit Buffer. The value sent out on the I2S bus will be:

TX_FIFO(Tail)

For reception of data, the 24-bit value received from the I2S bus will be loaded into the Receive Buffer. The 32-bit value sent back to the host processor on the DAT_O bus will be:

"SSSSSSSS" & RX_FIFO(Tail),

where S represents the sign bit: RX_FIFO(Tail)(23).

24 Bits (Left-Aligned).

The last mode is actually termed 32 bit mode.

For transmission of data, the host processor writes a 32-bit value appearing on the DAT_I bus. The lower 8-bits are ignored, with the remaining 24-bit data word (DAT_I(31..8)) loaded into the head of the Transmit Buffer. The value sent out on the I2S bus will be:

TX_FIFO(Tail)

For reception of data, the 24-bit value received from the I2S bus will be loaded into the Receive Buffer. The value sent back to the host processor on the DAT_O bus will be:

RX_FIFO(Tail) & "00000000"