Accessing Common-Bus Resources on the NanoBoard 3000

Frozen Content

Modified by Admin on Sep 13, 2017

Parent article: NanoBoard 3000 - Motherboard Resources

The following resources resident on a 3000-series NanoBoard share a common data bus, address bus and read and write enable lines:

Common-bus SRAM
Common-bus SDRAM
Common-bus Flash Memory
USB Hub (more specifically, the ISP1760 Hi-speed USB Host Controller)

The following table summarizes the available design interface components that can be placed from the FPGA NB3000 Port-Plugin.IntLib for access to, and communications with, any or all of these common-bus resources.

Component Symbol	Component Name	Description
	`SHARED_SRAM`	Place this component to interface to the motherboard's common-bus SRAM.
	`SHARED_SDRAM`	Place this component to interface to the motherboard's common-bus SDRAM.
	`SHARED_FLASH`	Place this component to interface to the motherboard's common-bus Flash memory.
	`SHARED_USB`	Place this component to interface to the motherboard's USB hub.
	`SHARED_SRAM_SDRAM`	Place this component to interface to the motherboard's common-bus SRAM and SDRAM.
	`SHARED_SRAM_FLASH`	Place this component to interface to the motherboard's common-bus SRAM and Flash memory.
	`SHARED_SRAM_USB`	Place this component to interface to the motherboard's common-bus SRAM and USB hub.
	`SHARED_SDRAM_FLASH`	Place this component to interface to the motherboard's common-bus SDRAM and Flash memory.
	`SHARED_SDRAM_USB`	Place this component to interface to the motherboard's common-bus SDRAM and USB hub.
	`SHARED_FLASH_USB`	Place this component to interface to the motherboard's common-bus Flash memory and USB hub.
	`SHARED_MEM`	Place this component to interface to the motherboard's common-bus SRAM, SDRAM and Flash memory resources.
	`SHARED_SRAM_SDRAM_USB`	Place this component to interface to the motherboard's common-bus SRAM and SDRAM memories, and also the USB hub.
	`SHARED_SRAM_FLASH_USB`	Place this component to interface to the motherboard's common-bus SRAM and Flash memories, and also the USB hub.
	`SHARED_SDRAM_FLASH_USB`	Place this component to interface to the motherboard's common-bus SDRAM and Flash memories, and also the USB hub.
	`SHARED_MEM_USB`	Place this component to interface to all of the motherboard's common-bus memory resources, and also the USB hub.

Only ONE common-bus related port component can be placed in an FPGA design. The design interface component used will depend on which particular common-bus resource(s) you wish to access, and how you have configured the Shared Memory Controller (WB_SHARED_MEM_CTRL_NB3000) – the intermediate design peripheral that sits between a processor in the design and the common-bus resource on the NanoBoard 3000.

The Shared Memory Controller has an option to control the visibility of unused pins – in terms of its interface to physical resources on the board. By default, this option is enabled and all pins of the interface will be shown. In terms of wiring, it is more convenient to leave all interface pins visible and wire all pins to the corresponding ports of the SHARED_MEM_USB port component. Those signals not required for the design, in accordance with the Controller's configuration, are internally handled. For example, active Low outputs relating to unused resource types are tied to '1', unused inputs are ignored and, if not using the SDRAM, the associated clock output signal will be tied to '0'.

However, you may not be using all four resources in your design, or may prefer to hide the 'clutter' of pins associated with resources that are not being used. You would then place the port component that truly corresponds to the resource(s) you are wishing to access, only wiring from the Shared Memory Controller to those pins of relevance. For the remaining pins of the port component chosen, use the orange guidance text on each unused port to terminate it correctly:

VCC – connect the unused port to VCC

GND – connect the unused port to GND