NanoBoard 3000 - Common-Bus SDRAM

Frozen Content

The NanoBoard 3000 includes Synchronous Dynamic RAM as part of the common-bus block of memory resources available to the on-board User FPGA device, or more specifically a programmed design therein.

Common-bus SDRAM available to an FPGA design.

The SDRAM is provided in the form of two 256Mbit, high-speed CMOS SDRAM devices. Each device is organized as 16M x 16 bits (4M x 16 bits x 4 banks) – combined together to give 16M x 32-bit storage (64MByte). Both devices are powered by the motherboard's 3.3V supply.

Location on Board

The common-bus SDRAM devices (designated U12 and U13) are located on the component side of the board, to the right of the User FPGA (U8) and immediately below the common-bus SRAM.

Schematic Reference

The common-bus SDRAM devices can be found on Sheet 27 (SDRAM_16Mx32.SchDoc, entitled 16M x 32 SDRAM TSOP54 x 2) of the motherboard schematics.

The common-bus memory block and interface wiring can be found on Sheet 25 (CommonMemory.SchDoc, entitled Common-Bus Memory Block).

Design Interface Component

A variety of design interface components are available from the FPGA NB3000 Port-Plugin.IntLib for access to, and communications with, any or all of the common-bus resources. The design interface component used will depend on which particular resource(s) you wish to access, and how you have configured the Shared Memory Controller – the intermediate design peripheral that sits between a processor in the design and the common-bus resource on the board. For more information, see Accessing Common-Bus Resources on the NanoBoard 3000.

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