WB_SHARED_MEM_CTRL - Configurable Wishbone Shared Memory Controller
Figure 1. WB_SHARED_MEM_CTRL - Configurable Wishbone Shared Memory Controller.
The Shared Memory Controller component (WB_SHARED_MEM_CTRL) provides an interface between a 32-bit processor and memories on a shared bus. The Controller provides access to, and use of, the following three different types of memory, each of which is multiplexed for access over shared data and address busses:
- Asynchronous Static RAM
- Single data rate Synchronous DRAM
- Parallel Flash memory
The Controller handles all multiplexing for you, negating the need for custom demultiplexing logic.
The WB_SHARED_MEM_CTRL is primarily designed to be used with the common-bus memories located on Altium's 3-connector daughter boards, such as the Xilinx Spartan-3 Daughter Board DB30. Provided the same pinout is used, the Controller could be used to interface to other memories of the types supported, and which are accessed using a shared bus architecture.
For information on the standard configurable memory controller – WB_MEM_CTRL – which can be used, for example, to access the independent SRAM on a 3-connector daughter board, see WB_MEM_CTRL - Configurable Wishbone Memory Controller.
Features at-a-glance
- Configure for use with up to three different memories – SRAM, SDRAM and Parallel Flash
- Completely configurable from the OpenBus System document or Schematic sheet
- Automatic sizing of input address line, based on specified physical memory size
- Wishbone-compliant
Availability
From an OpenBus System document, the Shared Memory Controller component can be found in the Memories region of the OpenBus Palette panel.
From a schematic document, the WB_SHARED_MEM_CTRL component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.
Designing with the WB_SHARED_MEM_CTRL
Use the following links to explore use of the WB_SHARED_MEM_CTRL in more detail: