WB_MEM_CTRL - Configurable Wishbone Memory Controller
Figure 1. WB_MEM_CTRL - Configurable Wishbone Memory Controller (Example SRAM Configuration shown).
The Memory Controller component (WB_MEM_CTRL) provides a simple, configurable interface, between a 32-bit processor and either single data rate Synchronous DRAM, Asynchronous Static RAM, 32-bit wide Block RAM (single or dual port), or parallel Flash memory.
If you need to access common-bus memory on a 3-connector daughter board, you need to use the WB_SHARED_MEM_CTRL peripheral. For more information, see WB_SHARED_MEM_CTRL - Configurable Wishbone Shared Memory Controller.
Features at-a-glance
- Simplified connection to processor's External Memory interface via a Wishbone Interconnect
- Completely configurable from the OpenBus System document or Schematic sheet
- Configurable as either SRAM, SDRAM, BRAM, or Parallel Flash Controller
- SDRAM Controller – interfaces to 8-, 16-, or 32-bit wide SDR SDRAM
- SRAM Controller – interfaces to 8-, 16-, or 32-bit wide asynchronous SRAM
- BRAM Controller – interfaces to 32-bit wide single or dual port Block RAM
- Flash Controller – interfaces to 8-, 16-, or 32-bit wide parallel Flash memory
- Automatic sizing of ADR_I input bus, based on specified physical memory size
- Wishbone-compliant.
Availability
From an OpenBus System document, the Memory Controller component can be found in the Memories region of the OpenBus Palette panel. Pre-configured BRAM, SDRAM and SRAM variants of the Controller are provided for convenience.
From a schematic document, the WB_MEM_CTRL component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.
Designing with the WB_MEM_CTRL
Use the following links to explore use of the WB_MEM_CTRL in more detail: