WB_MEM_CTRL - Pin Description (Flash-Configured)

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Figure 1. WB_MEM_CTRL configured as a Flash Controller.


The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to a single, 32-bit wide physical Parallel Flash memory device that is 1KB (256 x 32-bit) in size. Memory layout and size is specified as part of the Controller's configuration. Note also, that depending on the size of Flash memory that you specify the Controller to work with, the FLASH_A (FLASH0_A, FLASH1_A) and ADR_I signals will change in size accordingly.
 
Note: As there is no pre-configured Flash Memory component available for convenient placement in an OpenBus System, simply place one of the available SRAM, SDRAM, or BRAM memory components and configure as a Flash Memory controller in accordance with design requirements.

 
The following pin description is for the WB_MEM_CTRL when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to physical memory will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_MEM_CTRL Pin description (Flash-configured).
            Name            
Type
        Polarity/        
       Bus size        
Description
Control Signals
CLK_I
I
Rise
External (system) clock signal
RST_I
I
High
External (system) reset signal
Host Processor Interface Signals
STB_I
I
High
Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I
I
High
Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers
ACK_O
O
High
Standard Wishbone device acknowledgement signal. When this signal goes High, the Memory Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I
I
10-27
(see note 1)
Standard Wishbone address bus. Used to select an address in the connected Flash memory for writing to/reading from
DAT_O
O
32
Data to be sent to the connected Wishbone master device
DAT_I
I
32
Data received from the connected Wishbone master device
SEL_I
I
4/High
Select input, used to determine where data is placed on the DAT_O line during a Read cycle and from where on the DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24)
WE_I
I
Level
Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle.

0 = Read
1 = Write

Flash Memory Interface Signals
FLASH_D
IO
32
Memory Data Bus
FLASH_A
O
8-27
(see note 1)
Memory Address Bus
FLASH_CE
O
Low
Memory Chip Enable
FLASH_WE
O
Low
Memory Write Enable. Take this line Low to write to the memory location addressed by FLASH_A
FLASH_OE
O
Low
Memory Output Enable. Take this line Low to read from the memory location addressed by FLASH_A

Notes

  1. Depends on the size of physical Flash memory connected to.
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