WB_MEM_CTRL - Pin Description (SDRAM-Configured)
Figure 1. WB_MEM_CTRL configured as an SDRAM Controller.
The schematic symbol shown in Figure 1 represents the Memory Controller when configured to connect to a single, 32-bit wide physical SDRAM device that is 8MB (2M x 32-bit) in size. Memory layout and size is specified as part of the Controller's configuration. Note also, that depending on the size of SDRAM that you specify the Controller to work with, the ADR_I signal will change in size accordingly.
The following pin description is for the WB_MEM_CTRL when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to physical memory will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock signal |
| RST_I | I | High | External (system) reset signal |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the Memory Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 23-27 (see note 1) | Standard Wishbone address bus. Used to select an address in the connected SDRAM for writing to/reading from |
| DAT_O | O | 32 | Data to be sent to the connected Wishbone master device |
| DAT_I | I | 32 | Data received from the connected Wishbone master device |
| SEL_I | I | 4/High | Select input, used to determine where data is placed on the DAT_O line during a Read cycle and from where on the DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read |
| SDRAM Interface Signals | |||
| SDRAM_D | IO | 8/16/32 | Memory Data Bus |
| SDRAM_A | O | 13 | Memory Address Bus. This bus provides values used to select the row (SDRAM_RAS = 0, SDRAM_CAS=1) and column (SDRAM_RAS=1, SDRAM_CAS=0). The latter determines the address in the memory array from where to read (SDRAM_WE=0) or write (SDRAM_WE=1). |
| SDRAM_BA | O | 2 | Memory Bank Address |
| SDRAM_BE | O | 4/Low | Byte Enable signal. This signal is equivalent to SEL_I, but with the polarity reversed |
| SDRAM_RAS | O | Low | Row Address Select. When this signal is taken Low, the value on the SDRAM_A bus is used to select the bank and activate the required row. |
| SDRAM_CAS | O | Low | Column Address Select. When taken Low, the value on the SDRAM_A bus is used to select the bank and required column. A Read or Write will then be conducted from that memory location, depending on the state of SDRAM_WE. |
| SDRAM_WE | O | Level | Memory Write Enable. Determines whether the location in memory addressed by SDRAM_A is written to or read from: 0 = Read |
| SDRAM_CS | O | Low | Memory Chip Select |
| SDRAM_CLK | I | High | SDRAM Clock signal. The frequency of the clock signal must be the same as the speed of the memory. If the SDRAM is PC100 (100MHz), then a 100MHz clock signal must be made available within the FPGA to this input. |
| SDRAM_CLKE | O | High | Clock Enable |
Notes
- Depends on the size of physical SDRAM connected to.