WB_SHARED_MEM_CTRL - Pin Description
Frozen Content
The following pin description is for the WB_SHARED_MEM_CTRL when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to physical memory will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_SHARED_MEM_CTRL pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| SRAM_CLK_I (see note1) SDRAM_CLK_I FLASH_CLK_I | I | Rise | External (system) clock signal |
| SRAM_RST_I (see note 1) SDRAM_RST_I FLASH_RST_I | I | High | External (system) reset |
| MEM_CLK | I | Rise | SDRAM Clock signal. The frequency of this clock signal must be the same as the speed of the memory you are interfacing to. For example if the SDRAM is PC100 (100MHz), then a 100MHz clock signal must be made available within the FPGA to this input |
| Host Processor Interface Signals (SRAM) | |||
| SRAM_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| SRAM_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| SRAM_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| SRAM_ADR_I | I | 10-24 (see note 2) | Address bus, used to select an address in the connected memory for writing to/reading from |
| SRAM_DAT_O | O | 32 | Data to be sent to connected Wishbone Master device |
| SRAM_DAT_I | I | 32 | Data received from connected Wishbone Master device |
| SRAM_SEL_I | I | 4/High | Select input, used to determine where data is placed on the SRAM_DAT_O line during a Read cycle, and from where on the SRAM_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16-, or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| SRAM_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Host Processor Interface Signals (SDRAM) | |||
| SDRAM_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| SDRAM_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| SDRAM_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| SDRAM_ADR_I | I | 23-27 (see note 3) | Address bus, used to select an address in the connected memory for writing to/reading from |
| SDRAM_DAT_O | O | 32 | Data to be sent to connected Wishbone Master device |
| SDRAM_DAT_I | I | 32 | Data received from connected Wishbone Master device |
| SDRAM_SEL_I | I | 4/High | Select input, used to determine where data is placed on the SDRAM_DAT_O line during a Read cycle, and from where on the SDRAM_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16-, or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| SDRAM_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Host Processor Interface Signals (FLASH) | |||
| FLASH_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| FLASH_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| FLASH_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| FLASH_ADR_I | I | 25 | Address bus, used to select an address in the connected memory for writing to/reading from |
| FLASH_DAT_O | O | 32 | Data to be sent to connected Wishbone Master device |
| FLASH_DAT_I | I | 32 | Data received from connected Wishbone Master device |
| FLASH_SEL_I | I | 4/High | Select input, used to determine where data is placed on the FLASH_DAT_O line during a Read cycle, and from where on the FLASH_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16-, or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| FLASH_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Physical Memory Interface Signals | |||
| MEM_D | IO | 8/16/32 (see note 4) | Memory Data Bus |
| MEM_A | O | 24-26 (see note 5) | Memory Address Bus |
| MEM_W | O | Low | Memory Write Enable. Take this line Low to write to the memory location addressed by MEM_A |
| MEM_OE | O | Low | Memory Output Enable. Take this line Low to read from the memory location addressed by MEM_A. This signal applies to SRAM and Flash memory only |
| MEM_BE | O | 4/Low | Byte Enable. This signal is equivalent to SEL_I, but with the polarity reversed |
| MEM_SDRAM_CKE | O | High | SDRAM memory Clock Enable |
| MEM_SDRAM_RAS | O | Low | SDRAM memory Row Address Select. When this signal is taken Low, the value on the MEM_A bus is used to select the bank and activate the required row |
| MEM_SDRAM_CAS | O | Low | SDRAM memory Column Address Select. When this signal is taken Low, the value on the MEM_A bus is used to select the bank and column |
| MEM_SDRAM_E | O | Low | SDRAM memory Enable (chip select) |
| MEM_FLASH_BUSY | I | Low | Flash memory Busy |
| MEM_FLASH_RESET | O | Low | Flash memory external hardware reset |
| MEM_FLASH_E | O | Low | Flash memory Enable (chip select) |
| MEM_SRAM_E | O | Low | SRAM memory Enable (chip select) |
Notes
- In the OpenBus System, only single clock (SRAM_CLK_I) and reset (SRAM_RST_I) signals are used.
- Depends on the size of physical SRAM connected to.
- Depends on the size of the physical SDRAM connected to.
- The common MEM_D bus is 32 bits wide. However, if the option to Show unused pins – on the General page of the Configure Memory Controller dialog – is disabled, this width will change to reflect the layout/size of the memories being connected to.
- The common MEM_A bus is 24 bits wide. However, if the option to Show unused pins – on the General page of the Configure Memory Controller dialog – is disabled, this width will change to reflect the layout/size of the memories being connected to.