WB_JPGDEC_V2 - Wishbone JPEG Decoder (Version 2)

Frozen Content

Figure 1. WB_JPGDEC_V2 - Wishbone JPEG Decoder (Version 2).

The Wishbone JPEG Decoder component (WB_JPGDEC_V2) facilitates the decoding of baseline JPEG-compressed images (grayscale and color) into RGB565 pixel format output that can be written directly to screen display memory, or to a continuous external memory storage area.

The full JPEG image can be decoded, or only a specified area. The peripheral also supports block-based reading and writing.

The WB_JPGDEC_V2 component is functionally identical to the legacy WB_JPGDEC component. The only difference between these two components is that the SEL_I lines in the interface to the host processor have been removed in the WB_JPGDEC_V2. These lines are actually not used in the original WB_JPGDEC.

Features at-a-glance

  • Supports decoding of grayscale and color baseline (sequential) JPEG-formatted images
  • Output pixel format is Big-Endian, RGB565
  • Supports direct decoding to display memory
  • Ability to select an area of an image to decode
  • Block-based reading or writing – can be interrupt driven
  • 32-bit data interface to host processor
  • 32-bit DMA (Direct Memory Access) interface
  • Wishbone-compliant


From an OpenBus System document, the JPEG Decoder component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the WB_JPGDEC_V2 component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the WB_JPGDEC_V2

Use the following links to explore use of the WB_JPGDEC_V2 in more detail:

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