WB_JPGDEC_V2 - Pin Description
Frozen Content
The following pin description is for the WB_JPGDEC_V2 when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces.
Table 1. WB_JPGDEC_V2 pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock signal |
| RST_I | I | High | External (system) reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_JPGDEC_V2 (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 4 | Address bus, used to select an internal register of the device for writing to/reading from |
| DAT_O | O | 32 | Data to be sent to host processor |
| DAT_I | I | 32 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | High | Interrupt output line. This output will be taken High if any of the readable bits in the Status register become set (STATUS.8, STATUS6..0) and the corresponding bit in the Interrupt Mask register is also set. |
| DMA Interface Signals | |||
| M_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| M_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| M_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the connected Wishbone memory device has finished execution of the requested action and the current bus cycle is terminated |
| M_ADR_O | O | 32 | Standard Wishbone address bus, used to select an address of the connected Wishbone memory for writing to/reading from |
| M_DAT_I | I | 32 | Data received from external Wishbone memory |
| M_DAT_O | O | 32 | Data to be sent to external Wishbone memory |
| M_SEL_O | O | 4/High | Select output, used to determine where data is placed on the M_DAT_O line during a Write cycle, and from where on the M_DAT_I line data is accessed during a Read cycle. For the WB_JPGDEC_V2, only 32-bit data transfers to/from Wishbone memory are supported, meaning that all the lines go High during a Write or Read cycle |
| M_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |