WB_JPGDEC_V2 - Host to Controller Communications
Communications between a 32-bit host processor and the WB_JPGDEC_V2 are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
STATUS | If DAT_I(8) = '1':
STATUS(6..1) are cleared to '0'
If DAT_I(7) = '1':
STATUS.8 is cleared to '0'
STATUS[6..1] are cleared to '0'
If DAT_I(2) = '1':
STATUS.2 is cleared to '0'
If DAT_I(1) = '1':
STATUS.1 is cleared to '0' |
INTMASK | DAT_I(8..0) loaded into the Interrupt Mask register |
START_X | DAT_I(15..1) & "0" loaded into the START_X register |
START_Y | DAT_I(15..0) loaded into the START_Y register |
END_X | DAT_I(15..1) & "0" loaded into the END_X register |
END_Y | DAT_I(15..0) loaded into the END_Y register |
READ_ADDR | DAT_I(31..0) loaded into the Read Address register |
READ_COUNT | DAT_I(31..0) loaded into the Read Count register |
WRITE_STARTADDR | DAT_I(31..2) and "00" loaded into the Write Start Address register |
WRITE_ENDADDR | DAT_I(31..2) and "00" loaded into the Write End Address register |
WRITE_OFFSET | DAT_I(31..2) and "00" loaded into the Write Offset register |
WRITE_WIDTH | DAT_I(15..1) & "0" loaded into the Write Width register |
Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.
| Reading from... | Presents (to host processor)... |
|---|---|
STATUS | "000000000000000000000000" & 8-bit value from the Status register |
INTMASK | "000000000000000000000000" & 8-bit value from the Interrupt Mask register |
SIZE_X | "0000000000000000" & 16-bit value from the SIZE_X register |
SIZE_Y | "0000000000000000" & 16-bit value from the SIZE_Y register |
START_X | "0000000000000000" & 16-bit value from the START_X register |
START_Y | "0000000000000000" & 16-bit value from the START_Y register |
END_X | "0000000000000000" & 16-bit value from the END_X register |
END_Y | "0000000000000000" & 16-bit value from the END_Y register |
READ_ADDR | 32-bit value from the Read Address register |
READ_COUNT | 32-bit value from the Read Count register |
WRITE_STARTADDR | 32-bit value from the Write Start Address register |
WRITE_ENDADDR | 32-bit value from the Write End Address register |
WRITE_OFFSET | 32-bit value from the Write Offset register |
WRITE_WIDTH | "0000000000000000" & 16-bit value from the Write Width register |
WRITE_ADDR | 32-bit value from the Write Address register |