Wishbone Communications - 32-bit Processor to Slave Peripheral

Communications between a 32-bit host processor and a slave IO peripheral component are carried out over a standard Wishbone bus interface. The following sections detail the communication cycles involved between Host and Controller for writing to/reading from internal registers of the slave peripheral, which are accessible by the processor.

Writing to an Internal Register

Data is written from the host processor to an internal register in the slave peripheral, in accordance with the standard Wishbone data transfer handshaking protocol. The write operation occurs on the rising edge of the CLK_I signal and can be summarized as follows:

• The host presents the required 24-bit address based on the register to be written on its IO_ADR_O output and valid data on its IO_DAT_O output. It then asserts its IO_WE_O signal, to specify a write cycle

• The slave peripheral receives the n-bit address (where n is the width of its address bus) on its ADR_I input and, identifying the addressed register, prepares to receive data into that register

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The slave peripheral, which monitors its STB_I and CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by latching the data appearing at its DAT_I input into the target register and asserting its ACK_O signal – to indicate to the host that the data has been received

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time, the slave peripheral negates the ACK_O signal and the data transfer cycle is naturally terminated.

Reading from an Internal Register

Data is read from an internal register in accordance with the standard Wishbone data transfer handshaking protocol. The read operation, which occurs on the rising edge of the CLK_I signal, can be summarized as follows:

• The host presents the required 24-bit address based on the register to be read on its IO_ADR_O output. It then negates its IO_WE_O signal, to specify a read cycle

• The slave peripheral receives the n-bit address (where n is the width of its address bus) on its ADR_I input and, identifying the addressed register, prepares to transmit data from the selected register

• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The slave peripheral, which monitors its STB_I and CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by presenting the valid data on its DAT_O output and asserting its ACK_O signal – to indicate to the host that valid data is present

• The host, which monitors its IO_ACK_I input on each rising edge of the CLK_I signal, responds by latching the data appearing at its IO_DAT_I input and negating the IO_STB_O and IO_CYC_O signals. At the same time, the slave peripheral negates the ACK_O signal and the data transfer cycle is naturally terminated.