WB_JPGDEC_V2 - Interrupts

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Modified by Admin on Sep 13, 2017

The WB_JPGDEC_V2 provides for a single external interrupt line to the host processor. This line – INT_O – will be taken High if any of the following readable bits in the Status register become set:

jpgrdy (STATUS.0)

rempty (STATUS.1)

wfull (STATUS.2)

jpgerr (STATUS.3)

notjpg (STATUS.4)

corupt (STATUS.5)

unsup (STATUS.6)

rst (STATUS.8)

and provided that the corresponding bit in the Interrupt Mask register is also set.

Clearance of an interrupt requires that the Status register flag causing that interrupt be cleared. The following table summarizes how the interrupt state is cleared for each of these bits.

Table 1. Clearing interrupt causes.

Interrupt Cause	Action to clear interrupt
`jpgrdy`	This interrupt, if enabled, will be present as long as the WB_JPGDEC_V2 is in the ready state – after successful decoding of the JPEG image. It is cleared by writing '1' to either the `rst` or `start` bits in the Status register (STATUS.8 or STATUS.7 respectively).
`rempty`	Write new values to the READ_ADDR and READ_COUNT registers. Then write a '1' to this bit to clear it and resume decoding.
`wfull`	Write new values to at least one of the following registers: WRITE_STARTADDR, WRITE_ENDADDR, WRITE_OFFSET. Then write a '1' to this bit to clear it and resume decoding.
`jpgerr` `notjpg` `corupt` `unsup`	The `notjpg`, `corupt` and `unsup` flags generate interrupts for specific decoding errors. The `jpgerr` bit is purely a global flag for an error having occurred. It will become set, and remain set, while any of the specific error flags remain set. Clear all specific (and therefore global) error flags by writing '1' to either the `rst` or `start` bits in the Status register (STATUS.8 or STATUS.7 respectively).
`rst`	This interrupt, if enabled, will be present as long as the WB_JPGDEC_V2 is in the idle state. To clear, simply write to the `start` bit in the Status register (STATUS.7) to commence decoding and move out of the idle state.