WB_I2CM - Wishbone I2C Master Controller

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Figure 1. WB_I2CM - Wishbone I2C Master Controller.

The I2C Master Controller component (WB_I2CM) is used to facilitate data transfers over the I2C Bus and therefore ease communication with I2C devices external to the FPGA device. The I2C Bus is a two-wire, bi-directional serial bus that enables short distance data exchange between multiple devices connected to the bus.

Devices connected to the I2C bus can either be Master or Slave. The difference between the two lies primarily in the fact that a Master can take control of the serial clock and data lines (that constitute the I2C bus), changing their state in accordance with requests from the host processor.

Supply of the I2C soft core under the terms and conditions of the Altium End-User License Agreement does not convey nor imply any patent rights to the supplied technologies. Users are cautioned that a license from Royal Philips Electronics N.V. is required for any use covered by such patent rights, including the implementation of this core in an Integrated Circuit or any other device. For further information:


Features at-a-glance

  • I2C version 2.1 standard compliance
    • Transmission speed modes:
    • Standard Mode (up to 100kb/s)
    • Fast Mode (up to 400kb/s)
    • High-speed Mode (up to 3.4Mb/s)
  • Multimaster Mode
  • 7-bit slave addressing
  • Wishbone-compliant


From an OpenBus System document, the I2C Master Controller component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the WB_I2CM component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the WB_I2CM

Use the following links to explore use of the WB_I2CM in more detail:

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