WB_I2CM - Defining the Frequency of SCLK

The I2C Master Controller incorporates a 16-bit internal register, CLKDIV, whose stored value is used to scale the frequency of the clock signal generated by the Controller – SCLK. This register is further sub-divided into two 8-bit registers accessible by the host processor – CLOCK0 (low 8 bits) and CLOCK1 (high 8 bits).

The value you write to these registers depends on the ultimate frequency for SCLK that you wish to achieve. The following formula can be used to calculate the value for CLKDIV:

where,

CLK_I is the frequency of the Wishbone system clock

SCLK is the the desired frequency of the serial clock generated by the Controller.