WB_I2CM - Operational Overview

After an external reset, the WB_I2CM is effectively ready for use straight away.

Initialization

After a reset of the WB_I2CM, you may want to initialize the component and set it up ready in accordance with design requirements. Initialization can include:

• Enabling interrupts, if required, by setting the ien bit in the Control register (CONTROL.1)

• Writing the required 16-bit clock division value to the CLOCK0 (low byte) and CLOCK1 (high byte) registers.

Writing Data to a Slave Device

• Write the address for the required slave device to the DATA_WRITE register. Bits 7..1 are the address of the device. Bit 0 must be '0', to indicate a Write operation.

• Write to the Control register, setting the start and wr bits (CONTROL.6 and CONTROL.3 respectively). The content of the DATA_WRITE register will be loaded into the internal Shift Register.

• The Controller will then generate a START condition (once SDA and SCL are both High, taking the SDA line Low) and send the address for the required slave over the I2C Bus. After the START condition has been generated, the start bit in the Control register will be automatically cleared. Once the data (address) has finished transmission, the wr bit in the Control register will also be cleared.

• The Controller will generate an interrupt to the host processor – taking INT_O line High – (provided ien bit in the Control register is set), indicating that it has finished its current operation (i.e. START plus sending address of slave to initiate communications with).

• Interrogate the rxack bit in the Status register (STATUS.1). If this bit is '0', the addressed device has sent an acknowledgement and is connected for communications. If this bit is '1', then no device was found with the address used.

• Acknowledge the interrupt by setting the iack bit in the Control register (CONTROL.2).

• When successfully connected to the required slave device, write the data to be sent to the DATA_WRITE register and set the wr bit in the Control register. The content of the DATA_WRITE register will be loaded into the internal Shift Register.

• The Controller will transmit the data over the I2C Bus. Once done, the wr bit will be cleared. An interrupt will be generated to the processor to flag that the transfer has completed.

• Check the rxack bit in the Status register. If '0', the device received the data.

• Acknowledge the interrupt by setting the iack bit in the Control register.

• Write to the Control register, setting the stop bit. The Controller will then generate a STOP condition (once SDA and SCL are both Low, taking the SDA line High). The Controller is now finished with the I2C Bus and it is released.

• An interrupt will be generated to the processor to flag that the action has been performed – acknowledge by again setting the iack bit in the Control register.

Reading Data from a Slave Device

• Write the address for the required slave device to the DATA_WRITE register. Bits 7..1 are the address of the device. Bit 0 must be '1', to indicate a Read operation.

• Write to the Control register, setting the start and wr bits (CONTROL.6 and CONTROL.3 respectively). The content of the DATA_WRITE register will be loaded into the internal Shift Register.

• The Controller will then generate a START condition (once SDA and SCL are both High, taking the SDA line Low) and send the address for the required slave over the I2C Bus. After the START condition has been generated, the start bit in the Control register will be automatically cleared. Once the data (address) has finished transmission, the wr bit in the Control register will also be cleared.

• The Controller will generate an interrupt to the host processor – taking INT_O line High – (provided ien bit in the Control register is set), indicating that it has finished its current operation (i.e. START plus sending address of slave to initiate communications with).

• Interrogate the rxack bit in the Status register (STATUS.1). If this bit is '0', the addressed device has sent an acknowledgement and is connected for communications. If this bit is '1', then no device was found with the address used.

• Acknowledge the interrupt by setting the iack bit in the Control register (CONTROL.2).

• When successfully connected to the required slave device, set the rd bit in the Control register (Control.4).

• The Controller will receive data from the slave device. The data is shifted into the internal Shift Register.

• Once the byte of data is fully received, the Controller will either acknowledge/not acknowledge the slave device, depending on the state of the nack bit in the Control register (Control.7). The rd bit will be cleared and an interrupt will be generated to the processor to flag that the transfer has completed.

• The data will be transferred to the DATA_READ register, from where it can be accessed by the host processor.

• Acknowledge the interrupt by setting the iack bit in the Control register.

• Write to the Control register, setting the stop bit. The Controller will then generate a STOP condition (once SDA and SCL are both Low, taking the SDA line High). The Controller is now finished with the I2C Bus and it is released.

• An interrupt will be generated to the processor to flag that the action has been performed – acknowledge by again setting the iack bit in the Control register.

Sending/Receiving Multiple Bytes of Data

To send two data bytes to a slave I2C device and then read another two bytes from the same device the following steps need to be taken:

1. Write the address of the slave I2C device that you wish to write to into the DATA_WRITE register, with LSB cleared.
    
2. Set the following bits in the Control register: ien, wr, start
    
3. Wait for interrupt and read bit 1 (rxack) of the Status register to confirm the address is valid.
    
4. Acknowledge interrupt by setting iack bit in the Control register.
    
5. Write first data byte to the DATA_WRITE register.
    
6. Set the following bits in the Control register: ien, wr.
    
7. Wait for interrupt and confirm that the slave device received the first byte of data (by interrogating bit 1 (rxack) of the Status register).
    
8. Acknowledge interrupt by setting iack bit in the Control register.
    
9. Write second data byte to the DATA_WRITE register.
    
10. Set the following bits in the Control register: ien, wr
     
11. Wait for interrupt and confirm that the slave device received the second byte of data (by interrogating bit 1 (rxack) of the Status register).
     
12. Acknowledge interrupt by setting iack bit in the Control register.
     
13. Write the address of the same slave I2C device that you wish to read from into the DATA_WRITE register, with LSB set.
     
14. Set the following bits in the Control register: ien, wr, start.
     
15. Wait for interrupt and read bit 1 (rxack) of the Status register to confirm the address is valid.
     
16. Acknowledge interrupt by setting iack bit in the Control register.
     
17. Set the following bits in the Control register: ien, rd.
     
18. Wait for interrupt and read first byte of data from the DATA_READ register.
     
19. Acknowledge interrupt by setting iack bit in the Control register.
     
20. Set the following bits in the Control register: ien, rd, stop.
     
21. Wait for interrupt and read second byte of data from the DATA_READ register.

Clock Stretching

Some devices might not be ready to send data immediately after acknowledging being addressed by the I2C Master Controller. A good example is the MAX1037 device, which can be found on the NanoBoard. In one of its modes it needs to perform analog to digital conversion before it can send data to the I2C Master Controller. To this end, the Controller has support for clock stretching – whereby a slave device can insert wait states onto the I2C Bus while it prepares the data to be sent to the Controller. A wait state is defined as a slave I2C device driving the clock line low. In this instance, the I2C Master Controller should wait until the clock line is released before attempting to receive a data byte.