WB_I2CM - Host to Controller Communications

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Communications between a 32-bit host processor and the WB_I2CM are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Table 1 summarizes how the 8-bit data word from the host processor is used by each of the internal registers.

Table 1. Values written to internal registers during a write.
          Writing to...          
             Results in...             

CONTROL

DAT_I(7..0) loaded into the Control register

CLOCK0

DAT_I(7..0) loaded into Clock register 0 (effectively bits 7..0 of the CLKDIV register)

CLOCK1

DAT_I(7..0) loaded into Clock register 1 (effectively bits 15..8 of the CLKDIV register)

DATA_WRITE

DAT_I(7..0) loaded into the Data Write register

 
Table 2 summarizes the 'make-up' of the 8-bit data word that is read back from each register.

Table 2. Values read from internal registers during a read.
       Reading from...       
             Presents (to host processor)...             

CONTROL

8-bit value from the Control register

STATUS

8-bit value from the Status register

CLOCK0

8-bit value from Clock register 0 (effectively bits 7..0 of the CLKDIV register)

CLOCK1

8-bit value from Clock register 1 (effectively bits 15..8 of the CLKDIV register)

DATA_WRITE

8-bit value from the Data Write register

DATA_READ

8-bit value from the Data Read register

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