WB_PRTIO - Configurable Wishbone Parallel Port Unit

Figure 1. WB_PRTIO - Configurable Wishbone Parallel Port Unit.

The WB_PRTIO is a Wishbone-compliant, configurable parallel port unit, providing a simple register interface for storing data to be transferred to/from another device in a design. For example, when used with a Wishbone-compliant processor such as the TSK3000A, which does not have any on-core port interfaces, the unit provides a valuable new extension to the processor's feature set.

Features at-a-glance

• Three supported port types:
   
  • Input/Output
  • Output only
  • Tristate
     
• Ability to define 1, 2 or 4 port interfaces

• Three port data bus widths supported:
   
  • 8-bit
  • 16-bit
  • 32-bit
     
• Wishbone-compliant.

Availability

From an OpenBus System document, the Port IO component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the WB_PRTIO component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the WB_PRTIO

Use the following links to explore use of the WB_PRTIO in more detail: