WB_PRTIO - Pin Description
Frozen Content
The following pin description is for the WB_PRTIO when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_PRTIO pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (System) Clock |
| RST_I | I | High | External (System) Reset |
| Host Peripheral Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone-device acknowledgement signal. When this signal goes high, the Port Unit (Wishbone Slave) has finished execution of the requested action (i.e. transfer of data out to the host peripheral device (Wishbone Master)) and the current bus cycle is terminated |
| ADR_I (see note 1) | I | 0-3 (see note 2) | Address bus, used to select an internal register of the device for writing to |
| DAT_O | O | 8/16/32 (see note 3) | Data to be sent to host peripheral device |
| DAT_I | I | 8/16/32 | Data received from host peripheral device |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Port Input Bus Signals (see note 4) | |||
| PAI | I | 8/16/32 | Port A input bus |
| PBI (see note 5) | I | 8/16/32 | Port B input bus |
| PCI (see note 6) | I | 8/16/32 | Port C input bus |
| PDI (see note 6) | I | 8/16/32 | Port D input bus |
| Port Output Bus Signals | |||
| PAO | O | 8/16/32 | Port A output bus |
| PBO | O | 8/16/32 | Port B output bus |
| PCO | O | 8/16/32 | Port C output bus |
| PDO | O | 8/16/32 | Port D output bus |
| Port Output Tristate Signals (see note 7) | |||
| TRISA | O | 8/16/32 | External Tristate Buffer control output for Port A |
| TRISB | O | 8/16/32 | External Tristate Buffer control output for Port B |
| TRISC | O | 8/16/32 | External Tristate Buffer control output for Port C |
| TRISD | O | 8/16/32 | External Tristate Buffer control output for Port D |
The TRIS registers are simple registers – there is no internal connection between these registers and their corresponding port registers. You could use the TRIS registers in a device as simple output only ports.
The TRIS registers can also be used to provide the control signal to external tristate buffers, when you wish to use a bidirectional bus.
Notes
- The ADR_I signal applies only when the configuration of the WB_PRTIO component results in two or more internal registers. So for example, when configured as a 1-port, Output-only component, there will be no ADR_I line as the component contains only a single internal register.
- The number of address bits used in the ADR_I signal depends on the number of internal registers that are software-accessible. For example, a 2-port Output-only component contains 2 internal registers and so ADR_I will be 1 bit. A 4-port component of this type contains 4 internal registers, therefore requiring 2 address bits. For a 4-port Tristate-configured component, the internal register count is 8, which requires ADR_I to be 3 bits.
- The data width for all bus signals will depend on whether the component is configured to be 8-bit, 16-bit or 32-bit respectively.
- Port input bus signal(s) will only be available when the component is configured to be of type Input/Output or Tristate.
- Port B is available only when the component is configured to contain two or four ports.
- Ports C and D are only available when the component is configured to contain four ports.
- Tristate signal(s) will only be available if the component is configured to be of type Tristate.