WB_PRTIO - Host to Controller Communications

Frozen Content

Modified by Admin on Nov 6, 2013

Communications between the host peripheral (e.g. processor) and the WB_PRTIO component is carried out over the standard Wishbone bus.

The host peripheral device can write to/read from any of the WB_PRTIO's internal registers. Selection of a particular register is achieved by supplying the unique, binary ID address code of the register. This code is sent to the component and appears at the ADR_I input.

For the following port component configurations, only one internal register is present and therefore no address line is required:

WB_PRTIO configured as a 1-port, output only component
WB_PRTIO configured as a 1-port, input/output component.

Table 1 shows the unique address IDs for the registers when the component is configured to provide a 2-port unit of type Output or Input/Output, which possess two internal registers.

Table 1. 2-port Ouput or Input/Output component:
Internal register unique address IDs.

Register	Unique Register Address ID
PORTA	0
PORTB	1

Table 2 shows the unique address IDs for the registers when the component is configured to provide a 4-port unit of type Output or Input/Output, which possess four internal registers.

Table 2. 4-port Output or Input/Output component:
Internal register unique address IDs.

Register	Unique Register Address ID
PORT A	00
PORT B	01
PORT C	10
PORT D	11

When the WB_PRTIO component is configured as a Tristate port unit, an additional TRIS register is included for each port. Tables 3-5 show the unique address IDs for the registers in the 1-, 2- and 4-port variants of this type of unit respectively.

Table 3. 1-port Tristate component: Internal register
unique address IDs.

Register	Unique Register Address ID
PORTA	0
TRISA	1

Table 4. 2-port Tristate component: Internal register
unique address IDs.

Register	Unique Register Address ID
PORTA	00
PORTB	01
TRISA	10
TRISB	11

Table 5. 4-port Tristate component: Internal register
unique address IDs.

Register	Unique Register Address ID
PORTA	000
PORTB	001
PORTC	010
PORTD	011
TRISA	100
TRISB	101
TRISC	110
TRISD	111

Writing and Reading Internal Registers

Communications between a 32-bit host processor and the WB_PRTIO are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.