WB_USB - Host to Controller Communications

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Communications between a 32-bit host processor and the WB_USB are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.

Table 1 summarizes how the data from the host processor is used when writing to the WB_USB's internal register addresses.

Table 1. Values written to internal registers during a write.
            Writing to...            
            Results in...            

DAT_I(7..0) loaded into the Reset Cycles register


DAT_I(7..0) loaded into the Strobe Low Cycles register


DAT_I(7..0) loaded into the Strobe High Cycles register


DAT_I(7..0) loaded into the Write High Cycles register


DAT_I(7..0) loaded into the Address Setup Cycles register


DAT_I(7..0) loaded into the Read Status Cycles register

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