WB_USB - Accessible Internal Registers
Contents
The following sections detail the internal registers for the WB_USB that can be accessed from the host processor.
Reset Cycles Register (RESET_CYC)
Address: 10000
Access: Write
Value after Reset: 00011111
This register is used to store the value for the number of clock cycles to be observed when issuing a reset command to the CY7C68001 device. This value will be loaded into the Timer register (TIMER) when performing a Wishbone Write and the reset address is issued on the WB_USB's ADR_I line (ADR_I[4..0] = "01111").
The default value loaded into this register after a reset provides for 31+1 (N+1, where N is value after reset) cycles, which equates to 1600ns at 20MHz.
Strobe Low Cycles Register (STROBELOW_CYC)
Address: 10001
Access: Write
Value after Reset: 00000001
This register is used to store the value for the number of clock cycles to be observed when performing a Read, Write or Packet End with the CY7C68001 device and taking the corresponding USB_RD_N, USB_WR_N, or USB_PKTEND output of the WB_USB Low. This value will be loaded into the Timer register (TIMER). The applicable output will remain asserted (Low) until the designated time has elapsed.
The default value loaded into this register after a reset provides for 1+1 cycles, which equates to 50ns at 40MHz.
Strobe High Cycles Register (STROBEHIGH_CYC)
Address: 10010
Access: Write
Value after Reset: 00000001
This register is used to store the value for the number of clock cycles to be observed when performing a Read or Packet End with the CY7C68001 device and taking the corresponding USB_RD_N or USB_PKTEND output of the WB_USB High. This value will be loaded into the Timer register (TIMER). When the designated time has elapsed, the WB_USB will return to the 'idle' state.
The default value loaded into this register after a reset provides for 1+1 cycles, which equates to 50ns at 40MHz.
Write High Cycles Register (WRHIGH_CYC)
Address: 10011
Access: Write
Value after Reset: 00000011
This register is used to store the value for the number of clock cycles to be observed when performing a Write with the CY7C68001 device and taking the corresponding USB_WR_N output of the WB_USB High. This value will be loaded into the Timer register (TIMER). When the designated time has elapsed, the WB_USB will return to the 'idle' state.
The default value loaded into this register after a reset provides for 3+1 cycles, which equates to 100ns at 40MHz.
Address Setup Cycles Register (ADDRSETUP_CYC)
Address: 10100
Access: Write
Value after Reset: 00000001
This register is used to store the value for the number of clock cycles to be observed when performing a Read, Write or Packet End with the CY7C68001 device, prior to the corresponding USB_RD_N, USB_WR_N, or USB_PKTEND output of the WB_USB being taken Low. This value will be loaded into the Timer register (TIMER). When the designated time has elapsed, the applicable strobe output will be taken Low.
The default value loaded into this register after a reset provides for 1+1 cycles, which equates to 50ns at 40MHz.
Read Status Cycles Register (READSTATUS_CYC)
Address: 10101
Access: Write
Value after Reset: 00000001
This register is used to store the value for the number of clock cycles to be observed when reading back the status of the CY7C68001 device. This value will be loaded into the Timer register (TIMER) when performing a Wishbone Read and a valid Status address is issued on the WB_USB's ADR_I line (ADR_I[4..3] = "01", with ADR_I[2..0] used to specify which FIFO buffer you wish to interrogate the status for.
Once the designated time has elapsed, the WB_USB will return to the 'idle' state.
The default value loaded into this register after a reset provides for 1+1 cycles, which equates to 50ns at 40MHz.