WB_UART8_V2 - Host to Controller Communications
Communications between a 32-bit host processor and the WB_UART8_V2 are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 8-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
BRG[23..16] | DAT_I(7..0) loaded into bits 23..16 of the Baud Rate Generator register |
BRG[15..8] | DAT_I(7..0) loaded into bits 15..8 of the Baud Rate Generator register |
BRG[7..0] | DAT_I(7..0) loaded into bits 7..0 of the Baud Rate Generator register |
LINECTRL | DAT_I(7..0) loaded into the Line Control register |
INTMASKSET | DAT_I(7..0) is bitwise ORed with the current content of the Interrupt Mask register and the result loaded into the Interrupt Mask register |
INTMASKRST | DAT_I(7..0) is negated and then bitwise ANDed with the current content of the Interrupt Mask register and the result loaded into the Interrupt Mask register |
SBUF | "1" & DAT_I(7..0) loaded into the head of the Transmit Buffer (transmission of normal data) |
TXLOWMARK | DAT_I(7..0) loaded into the Transmit Buffer Low Watermark register |
RXHIGHMARK | DAT_I(7..0) loaded into the Receive Buffer High Watermark register |
RXLOWMARK | DAT_I(7..0) loaded into the Receive Buffer Low Watermark register |
RXDTO | DAT_I(7..0) loaded into the Receive Delay Timeout register |
ICD | DAT_I(7..0) loaded into the Inter Character Delay register |
BREAK | "0" & DAT_I(7..0) loaded into the head of the Transmit Buffer (initiating a BREAK) |
Table 2 summarizes the 'make-up' of the 8-bit data word that is read back from each register.
| Reading from... | Presents (to host processor)... |
|---|---|
BRG[23..16] | bits 23..16 from the Baud Rate Generator register |
BRG[15..8] | bits 15..8 from the Baud Rate Generator register |
BRG[7..0] | bits 7..0 from the Baud Rate Generator register |
LINECTRL | 8-bit value from the Line Control register |
STATUS | 8-bit value from the Status register |
INTMASK | 8-bit value from the Interrupt Mask register |
SBUF | 8-bit value for the received character currently at the tail of the Receive Buffer |
TXLOWMARK | 8-bit value from the Transmit Buffer Low Watermark register |
RXHIGHMARK | 8-bit value from the Receive Buffer High Watermark register |
RXLOWMARK | 8-bit value from the Receive Buffer Low Watermark register |
RXDTO | 8-bit value from the Receive Delay Timeout register |
ICD | 8-bit value from the Inter Character Delay register |