WB_UART8_V2 - Accessible Internal Registers

The following sections detail the internal registers for the WB_UART8_V2 that can be accessed from the host processor.

Baud Rate Generator Register (BRG)

Address: BRG[23..16] – 0000, BRG[15..8] – 0001, BRG[7..0] – 0010

Access: Read/Write

Value after Reset: 000000h

The upper (BRG[23..16]), middle (BRG[15..8]) and lower (BRG[7..0]) bytes of this register are accessed separately. The register's 24-bit value is used in the generation of the serial transmit and receive clocks.

The baud rate is generated based on the overflow rate of an internal 24-bit baud rate adder. This adder increments every timer tick with the 24-bit value set in the BRG register. When the most significant bit in the adder changes state from '0' to '1', the baud rate counter fires. A serial bit takes 8 clock cycles from this counter.

The value to be loaded into the BRG register can be calculated using the following expression:
 
BRG = (Baud Rate * 8000000h) / F _{CLK_I}
 

Line Control Register (LINECTRL)

Address: 0011

Access: Read/Write

Value after Reset: 80h

This 8-bit register is primarily used to control the hardware handshake between the WB_UART8_V2 and the remote device connected to its serial port. Additional bits are used to detect a received BREAK character and reflect the state of the RXD pin respectively. The latter can be used for autobaud detection algorithms.

Table 1. The LINECTRL register.

MSB                                                                                                                                                                                                                LSB
7	6	5	4	3	2	1	0
cts	break	rxdval	-	-	rtsval	forcerts	ctsen

Table 2. The LINECTRL register bit functions.

Bit	Symbol	Function
LINECTRL.7	cts	CTS Value flag. Returns current state of the CTS pin when read. This bit is ignored when writing to the register.
LINECTRL.6	break	BREAK Character Detection flag. Used to indicate the type of character at the tail of the Receive Buffer: 0 – character is a normal character 1 – character is a BREAK
LINECTRL.5	rxdval	RXD Value flag. Returns current state of the RXD pin when read. This bit is ignored when writing to the register.
LINECTRL.4	-	Not Used. Returns '0' when read
LINECTRL.3	-	Not Used. Returns '0' when read.
LINECTRL.2	rtsval	RTS Value bit. Controls the state of the RTS pin when the forcerts bit of this register is High: 0 – RTS taken Low 1 – RTS taken High
LINECTRL.1	forcerts	Force RTS bit. 0 – State of RTS pin is purely controlled based on the number of bytes in the Receive Buffer. If the number exceeds the high watermark defined by the RXHIGHMARK register, RTS goes High. RTS will automatically go Low when the number of bytes drops below the low watermark defined by the RXLOWMARK register. 1 – State of RTS pin is controlled by the value of the rtsval bit of this register.
LINECTRL.0	ctsen	Enable CTS bit. 0 – WB_UART8_V2 is free to transmit data without regard for the current state of the CTS pin 1 – WB_UART8_V2 must wait for the CTS pin to be taken Low by the connected serial station before transmission can proceed.

Status Register (STATUS)

Address: 0100

Access: Read Only

Value after Reset: 0Ah

This 8-bit register is used to determine the current state of the WB_UART8_V2 component.
 

Table 3. The STATUS register.

MSB                                                                                                                                                                                                                LSB
7	6	5	4	3	2	1	0
rxoverrun	rxhigh	rxnempty	rxtimeout	txshempty	txlow	txempty	txfull

Table 4. The STATUS register bit functions.

Bit	Symbol	Function
STATUS.7	rxoverrun	Receiver Overrun flag. Taken High if a character is received when the Receive Buffer is full.
STATUS.6	rxhigh	Receiver High flag. Taken High if the number of bytes in the Receive Buffer exceeds the high watermark defined by the RXHIGHMARK register.
STATUS.5	rxnempty	Receiver Not Empty flag. Taken High if the Receive Buffer is not empty.
STATUS.4	rxtimeout	Receiver Time-out flag. Taken High if the Receive Buffer is not empty and has not been read within time.
STATUS.3	txshempty	Transmitter Shift Register Empty flag. Taken High if the Transmitter shift register is empty.
STATUS.2	txlow	Transmitter Low flag. Taken High if the number of bytes in the Transmit Buffer is less than the low watermark defined by the TXLOWMARK register.
STATUS.1	txempty	Transmitter Empty flag. Taken High if the Transmit Buffer is empty.
STATUS.0	txfull	Transmitter Full flag. Taken High if the Transmit Buffer is full.

Interrupt Mask Register (INTMASK)

Address: 0101

Access: Read Only

Value after Reset: 00h

This 8-bit register is used to enable interrupt generation for each of the corresponding bits in the STATUS register. Provided bit INTMASK.n is High, an interrupt will be generated when the corresponding bit STATUS.n goes High.

A bit is set by writing a '1' to the corresponding bit in the Interrupt Mask Set register.

A bit is cleared by writing a '1' to the corresponding bit in the Interrupt Mask Reset register.
 

Table 5. The INTMASK register.

MSB                                                                                                                                                                                                                LSB
7	6	5	4	3	2	1	0
rxoverrun	rxhigh	rxnempty	rxtimeout	txshempty	txlow	txempty	txfull

Table 6. The INTMASK register bit functions.

Bit	Symbol	Function
INTMASK.7	rxoverrun	Enables interrupt generation for the Receiver Overrun condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.7) goes High.
INTMASK.6	rxhigh	Enables interrupt generation for the Receiver High condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.6) goes High.
INTMASK.5	rxnempty	Enables interrupt generation for the Receiver Not Empty condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.5) goes High.
INTMASK.4	rxtimeout	Enables interrupt generation for the Receiver Time-out condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.4) goes High.
INTMASK.3	txshempty	Enables interrupt generation for the Transmitter Shift Register Empty condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.3) goes High.
INTMASK.2	txlow	Enables interrupt generation for the Transmitter Low condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.2) goes High.
INTMASK.1	txempty	Enables interrupt generation for the Transmitter Empty condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.1) goes High.
INTMASK.0	txfull	Enables interrupt generation for the Transmitter Full condition. The interrupt will be generated if the corresponding bit in the Status register (STATUS.0) goes High.

Interrupt Mask Set Register (INTMASKSET)

Address: 0101

Access: Write Only

Value after Reset: 00h

This is not a register in the true sense of the word, but rather an address used to effectively enable (set to '1') corresponding interrupt enable bits in the Interrupt Mask register.

Note: Writing a '0' to a bit in this register will not change the status of the corresponding bit in the INTMASK register.
 

Table 7. The INTMASKSET register.

MSB                                                                                                                                                                                                                LSB
7	6	5	4	3	2	1	0
rxoverrun	rxhigh	rxnempty	rxtimeout	txshempty	txlow	txempty	txfull

Table 8. The INTMASKSET register bit functions.

Bit	Symbol	Function
INTMASKSET.7	rxoverrun	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Receiver Overrun condition.
INTMASKSET.6	rxhigh	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Receiver High condition.
INTMASKSET.5	rxnempty	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Receiver Not Empty condition.
INTMASKSET.4	rxtimeout	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Receiver Time-out condition.
INTMASKSET.3	txshempty	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Transmitter Shift Register Empty condition.
INTMASKSET.2	txlow	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Transmitter Low condition.
INTMASKSET.1	txempty	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Transmitter Empty condition.
INTMASKSET.0	txfull	Set this bit to set the corresponding bit in the INTMASK register and therefore enable interrupt generation for the Transmitter Full condition.

Interrupt Mask Reset Register (INTMASKRST)

Address: 0110

Access: Write Only

This is not a register in the true sense of the word, but rather an address used to effectively disable (clear to '0') corresponding interrupt enable bits in the Interrupt Mask register.

Note: Writing a '0' to a bit in this register will not change the status of the corresponding bit in the INTMASK register.

Table 9. The INTMASKRST register.

MSB                                                                                                                                                                                                                LSB
7	6	5	4	3	2	1	0
rxoverrun	rxhigh	rxnempty	rxtimeout	txshempty	txlow	txempty	txfull

Table 10. The INTMASKRST register bit functions.

Bit	Symbol	Function
INTMASKRST.7	rxoverrun	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Receiver Overrun condition.
INTMASKRST.6	rxhigh	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Receiver High condition.
INTMASKRST.5	rxnempty	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Receiver Not Empty condition.
INTMASKRST.4	rxtimeout	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Receiver Time-out condition.
INTMASKRST.3	txshempty	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Transmitter Shift Register Empty condition.
INTMASKRST.2	txlow	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Transmitter Low condition.
INTMASKRST.1	txempty	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Transmitter Empty condition.
INTMASKRST.0	txfull	Set this bit to clear the corresponding bit in the INTMASK register and therefore disable interrupt generation for the Transmitter Full condition.

Serial Data Buffer Register (SBUF)

Address: 0111

Access: Read/Write

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Buffers. Performing a Wishbone Write to the SBUF address loads data directly into the Transmit Buffer. If the Buffer is full, transmission may stop and the buffer content is overwritten.

Performing a Wishbone Read from the SBUF address retrieves data directly from the Receive Buffer. If no bytes are available in the Receive Buffer, the returned byte is invalid. Otherwise, the retrieved byte is removed from the buffer, effectively freeing up space.

If the connected serial device sends a break line condition, the break bit in the Line Control register (LINECTRL.6) will be set and the contents of the SBUF will contain the length of the break (in bit times).

Transmit Buffer Low Watermark Register (TXLOWMARK)

Address: 1000

Access: Read/Write

Value after Reset: 00h

For optimal performance, the Transmit Buffer should be filled at all times and the transmitter interrupt service should occur as little as possible. Therefore a low watermark can be set. When there are less bytes in the Transmit Buffer than indicated by this register, the corresponding txlow status flag (STATUS.2) will be set and an interrupt can be generated to indicate to the processor that it's time to refill the Transmit Buffer.
 

Receive Buffer Watermark Registers (RXHIGHMARK and RXLOWMARK)

Address: RXHIGHMARK – 1001, RXLOWMARK – 1010

Access: Read/Write

Value after Reset: RXHIGHMARK – FFh, RXLOWMARK – 00h

High and low watermarks can be defined for the Receive Buffer, which can then be used to control the state of the RST output line sent to the connected serial device from which data is being received. With the forcerts bit Low in the Line Control register (LINECTRL.1), if the number of bytes in the Receive Buffer exceeds the high watermark defined by the RXHIGHMARK register, RTS goes High. RTS will automatically go Low again when the number of bytes drops below the low watermark defined by the RXLOWMARK register.

Upon exceeding the high watermark, the rxhigh status flag will be set (STATUS.6). An interrupt can be generated provided that the corresponding interrupt enable bit in the Interrupt Mask register is set (INTMASK.6).
 

Receive Delay Timeout Register (RXDTO)

Address: 1011

Access: Read/Write

Value after Reset: 00h

This 8-bit register provides an 8-bit delay value used in the generation of the rxtimeout interrupt (if enabled). You are essentially specifying the number of bit cycles that can elapse since the last data received by the WB_UART8_V2. The delay time can be in the valid range 0 – 255.

After reception of the last data word (i.e. stop bit received) a delay counter is started. If another data word is received – heralded by the detection of another start bit – the delay counter is stopped. If, however, no further data is received, the delay counter will continue to increment on each change of the baudrate generator. If the Receive Buffer is not empty and the delay counter reaches the delay time specified by the Receive Delay Timeout register, then the rxtimeout interrupt will be generated provided:

• the rxtimeout bit in the Interrupt Mask register (INTMASK.4) is High and

• the rxtimeout bit in the Status register (STATUS.4) goes High.

Inter Character Delay Register (ICD)

Address: 1100

Access: Read/Write

Value after Reset: 00h

This register determines the minimum time the transmit line is kept idle between two characters, specified in bits. The delay time can be in the valid range 0 – 255.

BREAK Register (BREAK)

Address: 1101

Access: Write Only

This is not actually a register in the true sense of the word, but rather is a single address that is used to access and insert a BREAK condition into the Transmit Buffer. Performing a Wishbone Write to the BREAK address loads the BREAK value directly into the head of the Transmit Buffer. This value determines how long the transmit line will be kept active. The duration is defined in bits, and can be in the valid range 10 – 255 (i.e. the minimum length of a BREAK should be 10 bits).