WB_OWM - Host to Controller Communications
Communications between a 32-bit host processor and the WB_OWM are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes the values loaded into internal registers when writing to the WB_OWM.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
| CMD | DAT_I(7..0) loaded into the Command register |
| DATA | DAT_I(7..0) loaded into the Transmit Buffer |
| INTEN | DAT_I(7..0) loaded into the Interrupt Enable register |
| CLKDIV | DAT_I(7..0) loaded into the Clock Divider register |
Table 2 summarizes the values read back from the WB_OWM when performing a read.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
| CMD | 8-bit value from the Command register |
| DATA | 8-bit value from the Receive Buffer |
| INT | 8-bit value from the Interrupt register |
| INTEN | 8-bit value from the Interrupt Enable register |
| CLKDIV | 8-bit value from the Clock Divider register |