WB_OWM - Accessible Internal Registers
Contents
The following sections detail the internal registers for the WB_OWM that can be accessed from the host processor.
Command Register (CMD)
Address: 0h
Access: Read and Write
Value after Reset: 00h
This register is used to set the operational mode of the WB_OWM – either Standard 1-Wire mode, Search ROM Accelerator mode, or Overdrive mode. It is also use to control reset of the 1-Wire bus and/or the WB_OWM itself, as well as direct writing and reading to/from the 1-Wire bus.
Table 1. The CMD register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| od | - | rst | - | dqi | dqo | sra | 1wr |
| Bit | Symbol | Function |
|---|---|---|
| CMD.7 | od | Overdrive bit. If all slave devices on the 1-Wire bus support overdrive mode, setting this bit will allow high-speed communication.
This bit must be cleared when the WB_OWM is configured for standard 1-Wire communication. |
| CMD.6 | - | Not Used. Any value written will be ignored. Returns '0' when read |
| CMD.5 | rst | Reset bit. Setting this bit generates a software reset. Communications will be terminated and all internal state machines controlling communication over the 1-Wire bus will be reset. The WB_OWM's internal registers will not be reset and, with the possible exception of the Interrupt register, will retain their previous values.
This bit must be cleared for normal operation of the Controller. |
| CMD.4 | - | Not Used. Any value written will be ignored. Returns '0' when read |
| CMD.3 | dqi | DQ Input bit. Reflects the current state of the 1-Wire bus. Use this bit along with the
This bit is read only. As such, any value written to this bit will be ignored. |
| CMD.2 | dqo | DQ Output bit. This bit allows for direct control of the 1-Wire bus by the host processor. Used along with the
Setting this bit will take the bus Low, provided the |
| CMD.1 | sra | Search ROM Accelerator bit. Set this bit to place the WB_OWM in Search ROM Accelerator mode. This bit should be set after the following has been carried out:
|
| CMD.0 | 1wr | 1-Wire Reset bit. Set this bit to generate a reset on the 1-Wire bus. The
Upon completion of the reset, the |
Data Register (DATA)
Address: 1h
Access: Read/Write
Value after Reset: 00h
This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Buffers. Performing a Wishbone Write to the DATA address loads data directly into the Transmit Buffer. Performing a Wishbone Read from the DATA address retrieves data directly from the Receive Buffer.
When reading, the host processor must initiate the read by first writing to the Transmit Buffer with the value FFh. This value must be written each time you wish to read another byte of data from an external slave 1-Wire device on the bus. For further information on sending and receiving data over the 1-Wire bus, see Data Transfer over the 1-Wire Bus.
Interrupt Register (INT)
Address: 2h
Access: Read only
Value after Reset: 4Eh
This register is used to identify the cause of an interrupt. It contains flags associated with the transmit and receive buffers, as well as flags associated with the status of the 1-Wire bus and the WB_OWM device itself.
In total, there are six flags in this register that can be used to generate an interrupt to the processor on the INT_O line. For the interrupt to be generated, the corresponding bit in the Interrupt Enable register must also be set.
Reading the Interrupt register will result in the INT_O pin being placed in an inactive state, even if one or more interrupt-generating flags are not cleared.
| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| dqi | nbsy | sint | rbf | temt | tbe | pdr | pd |
| Bit | Symbol | Function |
|---|---|---|
| INT.7 | dqi | DQ Input bit. This bit is a direct copy of the |
| INT.6 | nbsy | Not Busy flag. Indicates the state of the WB_OWM:
0 = WB_OWM busy (i.e. a read, write, reset or slave interrupt is taking place) |
| INT.5 | sint | Slave Interrupt flag. This bit is set if the 1-Wire bus is held Low by a slave 1-Wire device (attached to the bus) for more than 960us. This bit is cleared upon reading the Interrupt register. |
| INT.4 | rbf | Receive Buffer Full flag. This bit will become set whenever the Receive Buffer contains a byte that the processor has yet to read. It will be cleared as soon as that byte of data is read. |
| INT.3 | temt | Transmit Shift Register Empty flag. This bit will be cleared when data has been shifted into the Transmit Shift register from the Transmit Buffer. It will become set again after the last bit of data in the byte has been shifted out onto the 1-Wire bus. |
| INT.2 | tbe | Transmit Buffer Empty flag. This bit will be cleared when data has been written by the processor into the Transmit Buffer. It will become set again after that byte of data has been transferred into the Transmit Shift register. |
| INT.1 | pdr | Presence Detect Result bit. This bit reflects the result of the presence detect read, after a 1-Wire reset has been issued and the time for a presence detect to have occurred has elapsed:
0 = a slave device was found |
| INT.0 | pd | Presence Detect flag. This bit will become set after a 1-Wire reset has been issued (
This bit is cleared upon reading the Interrupt register. |
The six interrupt generating flags are: nbsy, sint, rbf, temt, tbe and pd.
Interrupt Enable Register (INTEN)
Address: 3h
Access: Read and Write
Value after Reset: 00h
This register is primarily used to enable the corresponding interrupt bits in the Interrupt register. In addition, it provides bits to control the active level of the INT_O pin and an enable for the dqo bit in the Command register, when you want to control communications over the 1-Wire bus directly.
| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| dqoe | enbsy | esint | erbf | etemt | etbe | ias | epd |
| Bit | Symbol | Function |
|---|---|---|
| INTEN.7 | dqoe | DQ Output Enable bit. This bit is used to choose the source of control for the DQ bus:
0 = DQ bus is controlled automatically by the WB_OWM as normal |
| INTEN.6 | enbsy | Enable Not Busy Interrupt bit. Set this bit to enable interrupt generation for the Not Busy flag (INT.6). |
| INTEN.5 | esint | Enable Slave Interrupt bit. Set this bit to enable interrupt generation for the Slave Interrupt flag (INT.5). |
| INTEN.4 | erbf | Enable Receive Buffer Full Interrupt bit. Set this bit to enable interrupt generation for the Receive Buffer Full flag (INT.4). |
| INTEN.3 | etemt | Enable Transmit Shift Register Empty Interrupt bit. Set this bit to enable interrupt generation for the Transmit Shift Register Empty flag (INT.3). |
| INTEN.2 | etbe | Enable Transmit Buffer Empty Interrupt bit. Set this bit to enable interrupt generation for the Transmit Buffer Empty flag (INT.2). |
| INTEN.1 | ias |
0 – |
| INTEN.0 | epd | Enable Presence Detect Interrupt bit. Set this bit to enable interrupt generation for the Presence Detect flag (INT.0). |
Clock Divider Register (CLKDIV)
Address: 4h
Access: Read and Write
Value after Reset: 00h
The value written to this register is used to internally divide the incoming external system clock signal (CLK_I), to obtain a 1MHz base clock. This base clock frequency is used in the generation of all timings related to communications over the 1-Wire bus.
CLK_I must have a frequency in the range 3.2MHz to 128MHz (and preferably a 50/50 duty cycle).
| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| clken | - | - | div2 | div1 | div0 | pre1 | pre0 |
| Bit | Symbol | Function |
|---|---|---|
| CLKDIV.7 | clken | Clock Enable flag. This bit is set once the Clock Divider register is written with the divisor value required to obtain the base 1MHz clock signal. If this bit remains cleared, the WB_OWM will not function. |
| CLKDIV.6 | - | Not used. Any value written will be ignored. Returns '0' when read. |
| CLKDIV.5 | - | Not used. Any value written will be ignored. Returns '0' when read. |
| CLKDIV.4 | div2 | Value for the divider stage of the internal clock divider circuit: 000 = Divide by 1 |
| CLKDIV.3 | div1 | |
| CLKDIV.2 | div0 | |
| CLKDIV.1 | pre1 | Value for the prescaler stage of the internal clock divider circuit: 00 = 1 |
| CLKDIV.0 | pre0 |
Table 9 summarizes the values that can be loaded into the register, depending on the frequency of the incoming CLK_I signal. The register must be loaded with the applicable value after an external reset before communications over the 1-Wire bus can take place.
| For External Clock Frequency in the range... | Write CLKDIV register with... | Giving a Divider Ratio of... |
|---|---|---|
| 3.2MHz < CLK_I ≤ 4MHz | 08h | 4 |
| 4MHz < CLK_I ≤ 5MHz | 02h | 5 |
| 5MHz < CLK_I ≤ 6MHz | 05h | 6 |
| 6MHz < CLK_I ≤ 7MHz | 03h | 7 |
| 7MHz < CLK_I ≤ 8MHz | 0Ch | 8 |
| 8MHz < CLK_I ≤ 10MHz | 06h | 10 |
| 10MHz < CLK_I ≤ 12MHz | 09h | 12 |
| 12MHz < CLK_I ≤ 14MHz | 07h | 14 |
| 14MHz < CLK_I ≤ 16MHz | 10h | 16 |
| 16MHz < CLK_I ≤ 20MHz | 0Ah | 20 |
| 20MHz < CLK_I ≤ 24MHz | 0Dh | 24 |
| 24MHz < CLK_I ≤ 28MHz | 0Bh | 28 |
| 28MHz < CLK_I ≤ 32MHz | 14h | 32 |
| 32MHz < CLK_I ≤ 40MHz | 0Eh | 40 |
| 40MHz < CLK_I ≤ 48MHz | 11h | 48 |
| 48MHz < CLK_I ≤ 56MHz | 0Fh | 56 |
| 56MHz < CLK_I ≤ 64MHz | 18h | 64 |
| 64MHz < CLK_I ≤ 80MHz | 12h | 80 |
| 80MHz < CLK_I ≤ 96MHz | 15h | 96 |
| 96MHz < CLK_I ≤ 112MHz | 13h | 112 |
| 112MHz < CLK_I ≤ 128MHz | 1Ch | 128 |