WB_MULTIMASTER - Interfacing
Figure 1 shows an example of using a configurable Wishbone Multi-Master to share access to the same physical SRAM between one 32-bit processor (a Nios II) and, although not shown, two memory-based peripheral devices (a BT656 Video Capture Controller and a VGA32_16BPP Controller).
On the Master side, a Wishbone Interconnect component has been used to connect the processor to the Multi-Master component, due to its convenience in terms of wiring and handling of the address line mapping.
On the Slave side, the Multi-Master component connects to the physical memory through use of an appropriately-configured Memory Controller which, in this example, is configured to be an SRAM Controller.
The Wishbone Interconnect component can only be used with a 32-bit processor. It's use greatly simplifies the process of configuring the processor's address space. For more information, see Allocating Address Space in a 32-bit Processor.
Connecting to Multiple Slave Devices
Some designs may require shared processor access to more than one slave memory or peripheral device. By placing a Wishbone Interconnect component after the Wishbone Multi-Master component, it is possible to connect two processor masters to a whole bank of slave memory or peripheral devices. The devices would be mapped into the respective processor address spaces at identical locations.
Figure 2 shows an example of using both a Wishbone Multi-Master component and a Wishbone Interconnect component to allow two 32-bit processors (TSK3000As) to access a variety of physical slave memory devices.
In this example, the configuration of the Multi-Master makes it essentially a Dual Master device, except for the fact you can still nominate a master to have no delay in accessing the bus when the device is idle.
Another advantage of using a Multi-Master rather than a Dual Master is that it caters for expansion of the design. For example you might add one or more memory-based peripherals to a dual processor design, and those peripherals may also require shared access to the same external memory. If you have placed a Multi Master device from the start, it is simply a case of adding and configuring the required additional master interfaces to the existing device.
Sharing Peripheral Devices
Although the Wishbone Dual Master component can be used to share peripheral devices between two 32-bit processors, it cannot pass interrupts from a connected Wishbone Interconnect, through to those processors. The Wishbone Multi-Master on the other hand, can be configured to provide support for channeling interrupts and, from a design expansion perspective, is the prime candidate for use in a design.
Figure 3 shows an example of two 32-bit processors – a Nios II and a TSK3000A – sharing access to three different slave peripheral devices (a Keypad Controller, a Serial Port Unit and a VGA Controller). The latter two generate interrupts to the processors which, as indicated in the image, are channeled through the Multi-Master device.
For more information on connecting physical memory and peripheral I/O devices to a 32-bit processor, within an OpenBus System, see Connecting Slave Devices to a 32-bit Processor.