WB_IRRC - Host to Controller Communications
Communications between a 32-bit host processor and the WB_IRRC Controller are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the 32-bit data word from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
| CLK_DIV | DAT_I(23..0) loaded into the Clock Divider register |
| CTRL | the entire 32-bit value arriving on DAT_I loaded into the Control register |
| DATA | the entire 32-bit value arriving on DAT_I loaded into the internal TX_DATA register |
Table 2 summarizes the 'make-up' of the 32-bit data word that is read back from each register.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
| CLK_DIV | 24-bit value currently in the Clock Divider register (loaded into DATA_O(23..0)) |
| CTRL | 32-bit value currently in the Control register |
| STATUS | 32-bit value currently in the Status register |
| DATA | The internal register and value read depends on the current operating mode of the WB_IRRC:
|