WB_IRRC - Accessible Internal Registers

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The following sections detail the internal registers for the WB_IRRC, accessible from the host processor.

Clock Divider Register (CLK_DIV)

Address: 0h

Access: Read and Write

Value after Reset: FFFF_FFFFh

This register is used to hold a 24-bit value, required to generate the modulating carrier clock frequency used in sending/receiving IR pulses. For transmission, the resulting internal Pulse_Clock signal will be used to modulate the encoded message. For reception, it will be used to demodulate the received IR signal, stripping away the carrier and leaving just the encoded data.

The Pulse_Clock signal itself is generated using phase accumulation of a 24-bit adder. This adder increments on every tick of the CLK_I signal with the value stored in the CLK_DIV register. When the most significant bit in the adder changes state from '0' to '1', the Pulse_Clock signal changes phase.

The value to be loaded into the CLK_DIV register can be calculated using the following expression:

CLK_DIV = (f carrier * 8000000h) / f CLK_I

When configured to operate in NEC Encoder/Decoder mode, f carrier should be 38222Hz.

When configured to operate in Philips RC5 mode, f carrier should be 36000Hz.
 

Writing to the Clock Divider register will result in an internal reset of the WB_IRRC component. The Clock Divider register itself however, can only be reset through issue of an external hardware reset (RST_I taken High).

Control Register (CTRL)

Address: 1h

Access: Read and Write

Value after Reset: 0000_0000h

This register is used to set the operational mode of the WB_IRRC.

Table 1. The CTRL register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                               8
7
6
5
4
3
2
1
0
-
codec1
codec0
 - 
 - 
 - 
 - 
rxintrst
inten


Table 2. The CTRL register bit functions.
                 Bit                 
    Symbol    
Function
CTRL.31.. CTRL.8
-
Not Used.
CTRL.7
codec1
Codec selection bits. These bits ({{codec1:codec0}}) are used to set the operational mode of the peripheral:

00 = RAW Interface mode. Use this mode to transmit or receive IR data using any IR transmission protocol other than NEC or Philips RC5. IR data to be transmitted must be encoded in software. Likewise, received IR data must be decoded in software.

01 = NEC Encoder/Decoder mode. Use this mode to transmit or receive IR data using the NEC IR transmission protocol.

10 = RC5 Decoder mode: Use this mode when the data from the remote transmitter has been encoded using the Philips RC5 IR transmission protocol.

11 = Not used

CTRL.6
codec0
CTRL.5..CTRL.2
-
Not Used.
CTRL.1
rxintrst
Receiver Interrupt Reset / Reception Acknowledge bit. When using the WB_IRRC in interrupt-driven mode (interrupts enabled – inten bit of Control register set to '1') this bit should be written with '1' as soon as the embedded software on the processor is ready to receive another interrupt. Doing so will take the INT_O line Low and clear both this bit and also the rxint flag in the Status Register (STATUS.0).

When using the WB_IRRC in polling mode (interrupts disabled – inten bit of Control register cleared to '0') this bit should be written with '1' to acknowledge reception of the data by the processor. Doing so will clear this bit and also the rxint flag in the Status Register (STATUS.0).

CTRL.0
inten
Interrupt Enable bit. Set this bit High to enable generation of external interrupts to the processor.

Status Register (STATUS)

Address: 2h

Access: Read only

Value after Reset: 0000_0000h

This register is used to determine the current state of the WB_IRRC.

Table 3. The STATUS register.
MSB                                                                                                                                                                                                                LSB
31                                                                                                                                         5
4
3
2
1
0
-
txbusy
rxrepeat
rxoverrun
rxpdet
rxint


Table 4. The STATUS register bit functions.
                       Bit                       
    Symbol    
Function
STATUS.31.. STATUS.5
-
Not Used.
STATUS.4
txbusy
Transmit Busy flag. This bit is set upon writing to the WB_IRRC's Data register address, and loading new data into the internal TX_DATA register. This bit will automatically reset, once the peripheral has started to transmit the data. Wait until this bit clears before sending any further data.

When transmitting in NEC Encoder/Decoder mode, sending the same data to the WB_IRRC while it is currently transmitting (i.e. within 108ms) will cause a repeat code to be transmitted.

This bit permanently remains '0' when the WB_IRRC is configured to operate in RC5 Decoder mode.

STATUS.3
rxrepeat
Repeated Data Received flag. This bit is set if repeated data has been received.

When operating in NEC Encoder/Decoder mode, the setting of this bit indicates that a repeat code has been received.

When operating in RC5 Decoder mode, the setting of this bit means that the previously received data, including the Toggle bit (T), is the same as the current received data.

When operating in RAW Interface mode, the setting of this bit means that the length of the received mark/space is the same as the previously received mark/space.

STATUS.2
rxoverrun
Received Data Overrun flag. This bit will be set if new data is received without the previously received data being acknowledged. After reception of data, the rxint flag (STATUS.0) must be cleared to acknowledge its reception (by writing '1' to the rxintrst bit in the Control register (CTRL.1)). If the rxint bit is still set and new data is received, the rxoverrun flag will be set to indicate the overrun of received data. In all operating modes, the newly received data will be lost. In other words, no new data can be received and made available to the processor until the previous received data has been acknowledged.
STATUS.1
rxpdet
Receive Pulse Detect flag. This bit reflects the value of the data signal appearing at the RXD input, after it has been demodulated. If RXD is High, reflecting a space, then rxpdet will be '0'. Conversely, if RXD is Low, reflecting a mark (or pulse), then rxpdet will be '1'.
STATUS.0
rxint
Receive Interrupt flag. This bit is set if an edge is detected on the demodulated data signal (when in RAW Interface mode), or if valid command data is received (when in NEC Encoder/Decoder or RC5 Decoder modes).

Data Register (DATA)

Address: 3h

Access: Read and Write

Value after Reset: 0000_0000h

This is not actually a register in the true sense of the word, but rather is a single address that is used to access four internal storage registers – RAW_DATA, NEC_DATA, RC5_DATA and TX_DATA respectively. The internal register accessed depends on the WB_IRRC's current operational mode and whether you are performing a Wishbone Write operation (WE_I input High) or a Wishbone Read operation (WE_I input Low):

  • NEC Encoder/Decoder mode (WE_I input Low) – the NEC_DATA register is read, providing the output of the NEC Decoder Unit. Note that the 32-bit value will contain all bits sent from the remote controller (8 bit address, 8 bit address (inversed), 8 bit command, 8 bit command (inversed)).
  • NEC Encoder/Decoder mode (WE_I input High) – the TX_DATA register is written, providing the input of the NEC Encoder Unit. Note that the 32-bit value is sent as is. The txbusy bit in the Status register (STATUS.4) will be set upon writing to this register. Only when this bit is cleared are you allowed to send new data. Note that a repeat code will be sent if the same data is sent to the WB_IRRC within 108ms of sending the previous data.
  • RC5 Decoder mode (WE_I input Low) – the RC5_DATA register is read, providing the output of the RC5 Decoder Unit. Note that the value will contain all 14 bits sent from the remote controller (2 Start bits, Toggle bit, 5-bit address and the 6-bit command).
  • RAW Interface mode (WE_I input Low) – the RAW_DATA register is read, providing the output of the RAW Decoder Unit. The register gives the time (in periods of the carrier frequency) since the last transition of the demodulated RXD signal, which is reflected by the rxpdet bit in the Status register (STATUS.1). If rxpdet has changed from '0' to '1', the time will be reflected in the low-order word (RX_DATA(15..0)) and represents the length of the space. If rxpdet has changed from '1' to '0', the time will be reflected in the high-order word (RX_DATA(31..16)) and represents the length of the pulse burst (mark).
  • RAW Interface mode (WE_I input High) – the TX_DATA register is written, providing the input of the RAW Encoder Unit. The high-order word (TX_DATA(31..16)) should specify the time (in periods of the carrier frequency) for the pulse burst (mark). The low-order word (TX_DATA(15..0)) should specify the time (in periods of the carrier frequency) for the subsequent space. The txbusy bit in the Status register (STATUS.4) will be set upon writing to this register. Only when this bit is cleared are you allowed to send new data.
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