WB_DUALMASTER - Interfacing
Figure 1 shows an example of using a configurable Wishbone Dual Master component to connect two 32-bit processors (TSK3000As) to the Static RAM located on a daughter board.
On the Master side, Wishbone Interconnect components have been used to connect each processor to the Dual Master component, due to their convenience in terms of wiring and handling of the address line mapping.
On the Slave side, the Dual Master component connects to the physical memory through use of an appropriately-configured Memory Controller which, in this example, is configured to be an SRAM Controller.
The Wishbone Interconnect component can only be used with a 32-bit processor. It's use greatly simplifies the process of configuring the processor's address space. For more information, see Allocating Address Space in a 32-bit Processor.
Figure 2 illustrates an example design whereby a single physical memory device is shared between a TSK3000A processor and a memory-based VGA Controller. In such a design, the VGA Controller would be given higher priority with respect to memory access, otherwise effects such as screen flicker would be prevalent.
Connecting to Multiple Slave Devices
Some designs may require shared processor access to more than one slave memory or peripheral device. By placing a Wishbone Interconnect component after the Wishbone Dual Master component, it is possible to connect two processor masters to a whole bank of slave memory or peripheral devices. The devices would be mapped into the respective processor address spaces at identical locations. Figure 3 shows an example of using both a Wishbone Dual Master component and a Wishbone Interconnect component to allow two 32-bit processors (TSK3000As) to access a variety of physical slave memory devices.
Sharing Peripheral Devices
Although the Wishbone Dual Master component can be used to share peripheral devices between two processors, it cannot pass interrupts from a connected Wishbone Interconnect, through to those processors. If the peripheral devices being shared do not generate interrupts, or they are not being used, then use of a Wishbone Dual Master – in series with a Wishbone Interconnect – is fine.
Figure 4 shows an example of two 32-bit processors sharing access to three different slave peripheral devices (two parallel port units and an Ethernet Media Access Controller). The port units do not generate interrupts and the interrupt from the EMAC is not being used.
If you need to share peripherals between processors, then you should consider using a Wishbone Multi-Master component. It can be configured to have between two and eight masters, but more importantly, it also has support for interrupt channeling. For more information, see WB_MULTIMASTER - Configurable Wishbone Multi-Master.
For more information on connecting physical memory and peripheral I/O devices to a 32-bit processor, within an OpenBus System, see Connecting Slave Devices to a 32-bit Processor.