WB_BOOTLOADER - Host to Controller Communications
Communications between a 32-bit host processor and the WB_BOOTLOADER are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the byte of data from the host processor is used by each of the internal registers.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
| DATAOUT | io_DAT_I(7..0) loaded into the Parallel-to-Serial Data register |
| CSR | io_DAT_I(4..0) loaded into the Control/Status register |
| CDIV | io_DAT_I(7..0) loaded into the Clock Divider register |
Table 2 summarizes the 'make-up' of the 32-bit data word read back by the processor for each addressed register.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
| DATAIN | "000000000000000000000000" & 8-bit value currently in the Serial-to-Parallel Data register |
| CSR | "000000000000000000000000" & 8-bit value currently in the Control/Status register |
| CDIV | "000000000000000000000000" & 8-bit value currently in the Clock Divider register |
DATAOUT and DATAIN registers use the same address ("00"). Provided you are performing a write (io_WE_I input High), you will access the DATAOUT register. Provided you are performing a read (io_WE_I input Low), you will access the DATAIN register.