WB_BOOTLOADER - Accessible Internal Registers
Contents
The SPI Bootloader component contains four internal registers that are accessible by software, when the optional SPI Controller port is enabled – CSR, CDIV, DATAOUT, DATAIN. These registers allow the component to be used as an SPI Controller for communications between the processor in the design and external slave SPI devices.
Two additional registers – MEM_START and MEM_SIZE – relate to the bootloading functionality of the component. These registers are not accessible directly from the software. The values to these registers are written indirectly, through the associated configuration dialog for the device.
The following sections detail each of these registers.
Control/Status Register (CSR)
Address: 01
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to control aspects of the SPI Bootloader's operation, when used as an SPI Controller, and to determine the current state of the Controller.
Table 1. The CSR register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| busy | - | - | cpha | cpol | mode | cs | txen |
| Bit | Symbol | Function |
|---|---|---|
| CSR.7 | busy | Controller Busy status flag. This bit is set High whenever the Controller has started transmitting data to the target SPI peripheral device (i.e. FSM has left the IDLE state) |
| CSR.6 | - | Not used |
| CSR.5 | - | Not used |
| CSR.4 | cpha | SPI Clock Phase control bit. Determines the phase of the SPI_CLK signal, in relation to the transmitted data on the SPI_DOUT line:
0 – the first edge of the SPI_CLK signal is generated half an SPI_CLK period after the MSB of the data to be transmitted is made available on the SPI_DOUT line. Data will be latched on the leading edge and changed on the trailing edge.
1 – the first edge of the SPI_CLK signal is generated in conjunction with the MSB of the data to be transmitted being made available on the SPI_DOUT line. Data will be changed on the leading edge and latched on the trailing edge. |
| CSR.3 | cpol | SPI Clock Polarity control bit. Determines the idle (inactive) state for the SPI_CLK signal:
0 – SPI_CLK signal is inactive Low |
| CSR.2 | mode | SPI_MODE control bit. This bit is directly linked to the Controller's SPI_MODE output pin and can be used to control this signal as required |
| CSR.1 | cs | SPI_CS control bit. This bit is directly linked to the Controller's SPI_CS output pin and can be used to control this signal as required. When this signal is connected to the corresponding chip select input of a peripheral SPI device, taking the signal Low will enable that device for serial communications with the Controller. When the target SPI device is not selected (i.e. CSR.1 is '1'), it must tristate its data output |
| CSR.0 | txen | Transfer Enable control bit. Used to control state machine operation:
0 – Initiate serial communications transfer |
Bits 6 and 5 are ignored when writing to the register and return '0' when read. Bit 7 is Read-only.
Clock Divider Register (CDIV)
Address: 10
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to store a divisor for use in generation of the SPI_CLK signal, based on the external clock signal (io_CLK_I). As part of the SPI Clock Generation Unit, an internal counter is used to count up to the value written to the CDIV register. The next edge of SPI_CLK will only be generated when the internal counter reaches this divisor value.
The value written to the Clock Divider register can be anywhere in the valid range 0 to 2 8 - 1.
Table 3. The CDIV register
| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| div7 | div6 | div5 | div4 | div3 | div2 | div1 | div0 |
| Bit | Symbol | Function |
|---|---|---|
| CDIV.7 | div7 | Clock Divisor bit 7 |
| CDIV.6 | div6 | Clock Divisor bit 6 |
| CDIV.5 | div5 | Clock Divisor bit 5 |
| CDIV.4 | div4 | Clock Divisor bit 4 |
| CDIV.3 | div3 | Clock Divisor bit 3 |
| CDIV.2 | div2 | Clock Divisor bit 2 |
| CDIV.1 | div1 | Clock Divisor bit 1 |
| CDIV.0 | div0 | Clock Divisor bit 0 |
Parallel-to-Serial Data Register (DATAOUT)
Address: 00
Access: Write-only
Value after Reset: 00h
This 8-bit register is used to store the data to be transmitted to the target slave SPI device. The value written to this register can be anywhere in the valid range 0 to 2 8 - 1.
Table 5. The DATAOUT register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| data7 | data6 | data5 | data4 | data3 | data2 | data1 | data0 |
| Bit | Symbol | Function |
|---|---|---|
| DATAOUT.7 | data7 | Transmit data bit 7 |
| DATAOUT.6 | data6 | Transmit data bit 6 |
| DATAOUT.5 | data5 | Transmit data bit 5 |
| DATAOUT.4 | data4 | Transmit data bit 4 |
| DATAOUT.3 | data3 | Transmit data bit 3 |
| DATAOUT.2 | data2 | Transmit data bit 2 |
| DATAOUT.1 | data1 | Transmit data bit 1 |
| DATAOUT.0 | data0 | Transmit data bit 0 |
Serial-to-Parallel Data Register (DATAIN)
Address: 00
Access: Read-only
Value after Reset: 00h
This 8-bit register is used to store the data received from the target slave SPI device. The value in this register can be anywhere in the valid range 0 to 2 8 - 1.
Table 7. The DATAIN register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| data7 | data6 | data5 | data4 | data3 | data2 | data1 | data0 |
| Bit | Symbol | Function |
|---|---|---|
| DATAIN.7 | data7 | Received data bit 7 |
| DATAIN.6 | data6 | Received data bit 6 |
| DATAIN.5 | data5 | Received data bit 5 |
| DATAIN.4 | data4 | Received data bit 4 |
| DATAIN.3 | data3 | Received data bit 3 |
| DATAIN.2 | data2 | Received data bit 2 |
| DATAIN.1 | data1 | Received data bit 1 |
| DATAIN.0 | data0 | Received data bit 0 |
Memory Start Address Register (MEM_START)
This register is used to hold the value for the starting address in SRAM, from where the code copied from the serial Flash memory will be written, during the bootloading process. This value is specified as part of the SPI Bootloader device's configuration, using the Bootloader System Configuration dialog (see Configuration).
An additional internal register, MEM_CURRENT, is used to hold the current (SRAM) address that is being written to. After a reset, the MEM_CURRENT register will be loaded with the value stored in the MEM_START register. The actual address sent out on the me_ADR_O line to the physical SRAM device is:
me_ADR_O[19..0] = MEM_CURRENT[17..0] & "00"
Memory Size Register (MEM_SIZE)
This register is used to hold the value, in bytes, for the size of memory to be copied from the serial Flash memory to the SRAM, during the bootloading process. This value is specified as part of the SPI Bootloader device's configuration, using the Bootloader System Configuration dialog (see Configuration).
An additional internal register, WORD_COUNT, is used to hold the value for the remaining number of words to be copied from serial Flash memory. After a reset, the WORD_COUNT register will be loaded with the value stored in the MEM_SIZE register.