TMR3_W - Wishbone Dual Timer Unit

Figure 1. TMR3_W - Wishbone Dual Timer Unit.

The dual timer unit component (TMR3_W) is used to provide additional functionality to processors that do not inherently contain dedicated timing units. The TMR3_W can be configured as counters or timers and provideS four distinct modes of operation.

Features at-a-glance

• Four 8-bit registers providing dual timer functionality
   
  • TLA, THA – constituting Timer A
  • TLB, THB – constituting Timer B
     
• Configurable functionality – either Timer or Counter

• Four modes of operation for each Timer/Counter
   
  • Mode 0 : 13-bit Timer/Counter
  • Mode 1 : 16-bit Timer/Counter
  • Mode 2 : 8-bit auto-reload Timer/Counter
  • Mode 3 : Timer/Counter B stopped. Timer/Counter A functions as two independent 8-bit Timers/Counters
     
• External timer clocking inputs with rising edge detection

• Ability to control Timer clocking via external enable input

• Wishbone-compliant

Availability

From an OpenBus System document, the Dual Timer Unit component can be found in the Peripherals region of the OpenBus Palette panel.

From a schematic document, the TMR3_W component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation.

Designing with the TMR3_W

Use the following links to explore use of the TMR3_W in more detail: