TMR3_W - Timer Clocking and Interrupt Output Generation

Figure 1 presents a more detailed block diagram of the TMR3_W, showing the clocking of the two timers and the ultimate generation of the interrupt signal to the host processor – INT_O.

Figure 1. Timer clocking and interrupt output generation.

As can be seen in the diagram, both timers can be clocked by either an internal derivative of the external system clock, or by the rising edge of the relevant external clock input signal. The particular clocking signal used depends on whether the timer is configured in Timer or Counter mode respectively.

The clocking signal to Timer A is enabled when the tra bit in the Timer Control register (TCON.4)is '1' and either the gatea bit in the Timer Mode register (TMOD.3) is '0' or the external enable signal GATEA is '1'. If the gatea bit is set (1), Timer A will be enabled solely by the GATEA signal.

Similarly, the clocking signal to Timer B is enabled when the trb bit in the Tmer Control register (TCON.6) is '1' and either the gateb bit in the Timer Mode register (TMOD.7) is '0' or the external enable signal GATEB is '1'. To enable Timer B using solely the GATEB signal, the gateb bit must be set (1).