TMR3_W - Accessible Internal Registers
Contents
- Timer Control Register (TCON)
- Timer Mode Register (TMOD)
- Timer A Registers (TLA, THA)
- TLA Auto-Reload (Mode 2)
- TLA Register Active Clock Signal (Modes 0,1,3)
- THA Register Active Clock Signal
- Timer B Registers (TLB, THB)
- TLB Auto-Reload (Mode 2)
- TLB Register Active Clock Signal (Modes 0,1,3)
- THB Register Active Clock Signal
The following sections detail the internal registers for the TMR3_W that can be accessed from the host processor.
Timer Control Register (TCON)
Address: 0h
Access: Read/Write
Value after Reset: 00h
This register is used to control operation of the timers in the unit.
Table 1. The TCON register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| tfb | trb | tfa | tra | - | - | - | - |
| Bit | Symbol | Function |
|---|---|---|
| TCON.7 | tfb | Timer B overflow flag set by hardware when Timer B overflows. This flag should be cleared by the host processor.
This bit will be set under the following conditions:
|
| TCON.6 | trb | Timer B Run control bit. If cleared, Timer B stops. |
| TCON.5 | tfa | Timer A overflow flag set by hardware when Timer A overflows. This flag should be cleared by the host processor.
This bit will be set if Timer A is set to operate in Mode 0 or Mode 1 and either THA or TLA registers have reached the overflow state. |
| TCON.4 | tra | Timer A Run control bit. If cleared, Timer A stops. |
| TCON.3 | - | Not Used. Returns '0' when read. |
| TCON.2 | - | Not Used. Returns '0' when read. |
| TCON.1 | - | Not Used. Returns '0' when read. |
| TCON.0 | - | Not Used. Returns '0' when read. |
Timer Mode Register (TMOD)
Address: 1h
Access: Read/Write
Value after Reset: 00h
This register is used to determine whether Timer or Counter operation is used, which mode of operation is used and also whether external gating is enabled for each timer/counter.
Table 3. The TMOD register.
| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| gateb | ctb | m1b | m0b | gatea | cta | m1a | m0a |
| Bit | Symbol | Function |
|---|---|---|
| TMOD.7 | gateb | Timer B Gate bit. If set, enables external gate control (pin GATEB for Timer/Counter B). When GATEB is high, and the |
| TMOD.6 | ctb | Timer B Counter/Timer bit. Selects Timer or Counter operation for Timer B. When set to 1, a Counter operation is performed, when cleared to 0, the register will function as a Timer. |
| TMOD.5 | m1b | Timer B Mode Select bit 1. See table 5 for explanation of modes. |
| TMOD.4 | m0b | Timer B Mode Select bit 0. See table 5 for explanation of modes. |
| TMOD.3 | gatea | Timer A Gate bit. If set, enables external gate control (pin GATEA for Timer/Counter A). When GATEA is high, and the |
| TMOD.2 | cta | Timer A Counter/Timer bit. Selects Timer or Counter operation for Timer A. When set to 1, a Counter operation is performed, when cleared to 0, the register will function as a Timer. |
| TMOD.1 | m1a | Timer A Mode Select bit 1. See table 5 for explanation of modes. |
| TMOD.0 | m0a | Timer A Mode Select bit 0. See table 5 for explanation of modes. |
| m1a/m1b | m0a/m0b | Mode | Function |
|---|---|---|---|
| 0 | 0 | Mode 0 | 13-bit Timer/Counter, with 5 lower bits in TLA or TLB register and 8 bits in THA or THB register (for Timer A and Timer B, respectively). The 3 high order bits of TLA and TLB are held at zero. |
| 0 | 1 | Mode 1 | 16-bit Timer/Counter. |
| 1 | 0 | Mode 2 | 8-bit auto-reload Timer/Counter. The reload value is kept in THA or THB, while TLA or TLB is incremented after every period of the external clock signal (CLK_I). When TLA/TLB overflows, a value from THA/THB is copied to TLA/TLB. |
| 1 | 1 | Mode 3 | If Timer B
TLA operates as an 8-bit timer/counter
Both registers function independently of each other. |
When Timer A is configured in mode 3:
- TLA is affected by the
tra(TCON.4) andgatea(TMOD.3) bits, and sets thetfaflag (TCON.5) on overflow.
- THA is affected by the
trb(TCON.6) bit, and sets thetfbflag (TCON.7) on overflow.
Timer A Registers (TLA, THA)
Address: TLA – 2h; THA – 4h
Access: Read/Write
Value after Reset: 00h
These two 8-bit registers – Timer A Low (TLA) and Timer A High (THA) – constitute the 16-bit Timer A register/Counter. TLA represents the low 8 bits, while THA represents the high 8 bits.
For information on how these two registers are used depending on operational mode selected for the Timer, refer back to Table 5.
TLA Auto-Reload (Mode 2)
When Timer A is currently in Mode 2 and the TLA register reaches the overflow state, the reload value stored in the THA register will be automatically loaded into the TLA register.
TLA Register Active Clock Signal (Modes 0,1,3)
The content of the TLA register will be incremented by 1 when the register's clock input (TLA_CLK_I) goes High. The nature of the increment depends on the current mode setting for Timer A:
- In Mode 0, the value represented by the low 5 bits of TLA is incremented by 1 – bits 7-5 are held constantly at 0
- In Modes 1 and 3, the full value in the TLA register is incremented by 1.
THA Register Active Clock Signal
The content of the THA register will be incremented by 1 when the register's clock input (THA_CLK_I) goes High.
Timer B Registers (TLB, THB)
Address: TLB – 3h; THB – 5h
Access: Read/Write
Value after Reset: 00h
These two 8-bit registers – Timer B Low (TLB) and Timer B High (THB) – constitute the 16-bit Timer B register/Counter. TLB represents the low 8 bits, while THB represents the high 8 bits.
For information on how these two registers are used depending on operational mode selected for the Timer, refer back to Table 5.
TLB Auto-Reload (Mode 2)
When Timer B is currently in Mode 2 and the TLB register reaches the overflow state, the reload value stored in the THB register will be automatically loaded into the TLB register.
TLB Register Active Clock Signal (Modes 0,1,3)
The content of the TLB register will be incremented by 1 when the register's clock input (TLB_CLK_I) goes High. The nature of the increment depends on the current mode setting for Timer B:
- In Mode 0, the value represented by the low 5 bits of TLB is incremented by 1 – bits 7-5 are held constantly at 0
- In Modes 1 and 3, the full value in the TLB register is incremented by 1.
THB Register Active Clock Signal
The content of the THB register will be incremented by 1 when the register's clock input (THB_CLK_I) goes High AND the current mode setting for Timer B is either 0, 1 or 3.