TERMINAL - Host to Controller Communications
Communications between a 32-bit host processor and the Terminal module are carried out over a standard Wishbone bus interface. For a generic summary of the communication cycles involved between Host and Controller for writing to/reading from the accessible internal registers, see Wishbone Communications - 32-bit Processor to Slave Peripheral.
Table 1 summarizes how the byte of data from the host processor is used when writing to the TERMINAL instrument's internal register addresses.
Table 1. Values written to internal registers during a write.| Writing to... | Results in... |
|---|---|
INTCTRL | DAT_I(7..0) loaded into the INTCTRL register |
INTSTATUS | If DAT_I(5) = '1':
STATUS.5 is cleared to '0'
If DAT_I(1) = '1':
STATUS.1 is cleared to '0' |
SBUF | DAT_I(7..0) loaded into the Transmit Buffer |
Table 2 summarizes the 'make-up' of the byte of data that is read back from each register.
Table 2. Values read from internal registers during a read.| Reading from... | Presents (to host processor)... |
|---|---|
STATUS | 8-bit value currently in the STATUS register |
INTCTRL | "00000000" |
INTSTATUS | 8-bit value currently in the STATUS register |
SBUF | Next byte of data in the Receive Buffer |