TERMINAL - Accessible Internal Registers

Frozen Content

Modified by Admin on Sep 13, 2017

The following sections detail the internal registers for the Terminal module. Under the bonnet, the device uses the same register addresses as those for the WB_UART8. However, only the registers and bits pertinent to the function of the Terminal module are detailed as part of this document.

Status Register (STATUS)

Address: 0100b

Access: Read-only

Value after Reset: 00001010b

This 8-bit register is used to determine the current state of the Terminal module.

Table 1. The STATUS register.

MSB LSB
7	6	5	4	3	2	1	0
rxfull	-	rxnempty	-	txshempty	-	txempty	txfull

Table 2. STATUS register bit functions.

Bit	Symbol	Function
STATUS.7	rxfull	Receiver Full flag. Taken High if the Receive Buffer is full.
STATUS.6	-	Not used. Returns '0' when read.
STATUS.5	rxnempty	Receiver Not Empty flag. Taken High if the Receive Buffer is not empty.
STATUS.4	-	Not used. Returns '0' when read.
STATUS.3	txshempty	Transmitter Shift Register Empty flag. Taken High if the Transmitter shift register is empty.
STATUS.2	-	Not used. Returns '0' when read.
STATUS.1	txempty	Transmitter Empty flag. Taken High if the Transmit Buffer is empty.
STATUS.0	txfull	Transmitter Full. Taken High if the Transmit Buffer is full.

Interrupt Control Register (INTCTRL)

Address: 0101b

Access: Read/Write

Value after Reset: 00000000b

This 8-bit register is used to enable interrupt generation for each of the corresponding bits in the STATUS register. Provided bit INTCTRL.n is High, an interrupt will be generated when the corresponding bit STATUS.n goes High.

Table 3. The INTCTRL register.

MSB LSB
7	6	5	4	3	2	1	0
-	-	rxnempty	-	-	-	txempty	-

Table 4. INTCTRL register bit functions.

Bit	Symbol	Function
INTCTRL.7	-	Not used.
INTCTRL.6	-	Not used.
INTCTRL.5	rxnempty	Enables interrupt generation for Receiver Not Empty flag (STATUS.5).
INTCTRL.4	-	Not used.
INTCTRL.3	-	Not used.
INTCTRL.2	-	Not used.
INTCTRL.1	txempty	Enables interrupt generation for Transmitter Empty flag (STATUS.1).
INTCTRL.0	-	Not used.

Interrupt Status Register (INTSTATUS)

Address: 0110b

Access: Read/Write

This is not actually a register in the true sense of the word, but rather is a single address with which to effectively write to the Status register to clear flags after a generated interrupt:

After a transmitter interrupt, whereby the txempty and txshempty bits of the Status register (STATUS.1 and STATUS.3) are taken High, writing to the INTSTATUS address with DAT_I(1) = '1' will clear both the txempty and the txshempty flags in the Status register.

After a receiver interrupt, whereby the rxnempty and rxfull bits of the Status register (STATUS.5 and STATUS.7) are taken High, writing to the INTSTATUS address with DAT_I(5) = '1' will clear both the rxnempty and the rxfull flags in the Status register.

Performing a Wishbone Read from the INTSTATUS address retrieves data directly from the Status register.

Serial Data Buffer Register (SBUF)

Address: 0111b

Access: Read/Write

This is not actually a register in the true sense of the word, but rather is a single address that is used to access the Transmit and Receive Buffers. Performing a Wishbone Write to the SBUF address loads data directly into the Transmit Buffer. If the Buffer is full, transmission may stop and the buffer content is overwritten.

Performing a Wishbone Read from the SBUF address retrieves data directly from the Receive Buffer. If no bytes are available in the Receive Buffer, the returned byte is invalid. Otherwise, the retrieved byte is removed from the buffer, effectively freeing up space.