Placing the Logic Analyzer
The configurable LAX instrument provides an efficient means of analyzing the logical levels of signals in a design. The figure below shows a simple example of how the device is wired into a design.
In the example circuit above the LAX instrument is configured for 16-bit capture, using 1Kx16 internal storage memory. A single signal set has been defined - Binary Counter - with all 16 available input channels in the set (Count15..0) used to monitor the corresponding outputs of a 16-bit cascadable binary counter.
The capture clock signal, CLK_CAP, is derived from the external system clock. Notice that a divide-by-4 clock divider has been used. This makes the CLK_CAP signal four times slower than the system clock. CLK_CAP must be slower than CLK, otherwise the Logic Analyzer will not capture data at all. To capture data at the same rate as CLK, enable the Capture Every Clock Edge option in the Logic Analyzer - Options dialog.
Note: In order to communicate with soft devices in a design (processors and/or virtual instruments) you must enable the soft devices JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus-Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in the figure below.
These devices can be found in the FPGA NB2DSK01 Port-Plugin (FPGA NB2DSK01 Port-Plugin.IntLib) and FPGA Generic (FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of the installation.
Hierarchical Monitoring using Instrument Probes
To simplify the task of connecting the net of interest to a logic analyzer, Altium Designer provides the instrument probe directive. An instrument probe directive instructs the system to connect the net to which it is attached directly to the monitoring instrument (e.g. a logic analyzer) without having to explicitly wire that net up through the design hierarchy to the sheet with the instrument on it.
Simply place an instrument probe directive at the point of interest, then define a value for its InstrumentProbe parameter. Enter a meaningful name for the probe point, for example the name of the associated net or the particular signal being monitored. Then, connect a wire to the required input of the monitoring instrument and attach a net label to the wire, the name of which is the same name you have defined for the InstrumentProbe parameter.
If the instrument probe directive is placed on a net that connects to an FPGA pin, it can be used to monitor the status of that pin directly on the schematic sheet, as well as being used as an input source to a monitoring instrument. The former is achieved using the directive's ProbeValueDisplay parameter.
When an instrument probe is attached to a bus, the entire bus is taken up to the top-level sheet, irrespective of the name you assign to the InstrumentProbe parameter. When you add a net label to the input for the monitoring instrument, you must define the bus width required. For example, you may have attached an instrument probe to a bus with identifier Port1_Out7..0 on a lower level sheet. The value for the InstrumentProbe parameter could be simply set to Port1_Out. The entire bus will be connected up to the sheet with the monitoring device (e.g. a LAX). Should you wish to wire up the entire bus as an input signal to the device, you would place a bus to the required input and add a net label of Port1_Out7..0. If you only wanted a particular signal or range of signals from the bus, you can simply define the width required in the attached net label.