Logic Analyzer

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An example of the configurable Logic Analyzer.

The configurable Logic Analyzer instrument (LAX) is capable of supporting 8-, 16-, 32- or 64-bit capture. The instrument can be configured to use predefined internal storage memories for captured data, or to connect to an external block of RAM. Incorporating an internal multiplexer, the instrument can be configured to monitor any number of nets and buses – fed into the device as signal sets – with one set of signals nominated to be captured while the circuit is under test. The instrument also offers the ability to interpret the data being captured as the code under execution, using data disassembly.

Features at-a-glance

  • Ability to define up to 16 signal sets for monitoring, select and change the monitored set at run-time.
  • Supports 8-, 16-, 32- or 64-bit capture width – how many signal channels each defined signal set can contain - automatically selected based on the requirements of all defined signal sets
  • Ability to store captured samples in internal or external memory, with an indication of the memory size required
    • Internal Memory: Choose from 1K, 2K or 4K samples
    • External Memory: Choose from 16 samples all the way up to 1024K samples (4 to 20 bit address bus respectively)
  • Indication of used width for a signal set and prevention to exceed the maximum 64-bit capture width
  • Ability to assign wave styles to signals (for display in the Digital Waveform Viewer)
  • Ability to trigger off one signal set and capture data from same or different signal set
  • Ability to use each configuration in split mode
  • External (Hardware) or internal (Software) triggering
  • Ability to capture data at rate of system clock
  • Ability to keep the instrument 'armed' indefinitely
  • Ability to disassemble captured data
  • Analog and digital waveform generation
    • Support for continuous data capture from within waveform views
    • Cursor synchronization between waveform views
    • Pan and zoom synchronization between waveform views
  • Connect nets and buses to the LAX from anywhere in the design by using Instrument Probe Directives

Using the Configurable Logic Analyzer

  1. The Configurable LAX component is in the FPGA Instruments integrated library (FPGA Instruments.IntLib), located in the \Library\Fpga folder of the installation. The instrument is placed on the schematic, as shown in step (1) of the figure below, and wired into the circuit. Right-click on the component on the schematic to Configure the signal sets and other options.
    Main articles: Placing the Logic Analyzer, Configuring the Logic Analyzer
  2. When the design is built (compiled, synthesized and a place and route is performed), the logic for the LAX is included with the design and downloaded into the target FPGA. The LAX is then accessed during run-time via the Altium Designer Devices view, double-clicking on the icon for the LAX will open the LAX Instrument.
    Main article: Operating the Logic Analyzer
  3. From the LAX instrument, you have access to the LAX panel, where triggering is configured and numerical result data is displayed. From the LAX instrument you can also display the results as digital or analog waveforms.
    Main articles: Viewing Data Captured by the Logic Analyzer, LAX

(1) Place and configure the LAX, (2) access it during run-time in the Devices view, (3) then display the result in tabular form or as waveforms.

See Also

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