LAX - Pin Description

Logic Analyzer Input Signals

CLK

I

Rise

External system clock

CLK_CAP

I

Rise

Capture Clock input. The capture clock must be slower than the external system clock. If the Capture Every Clock Edge option is enabled in the Logic Analyzer - Options dialog (see Capturing Data), this input is ignored and data will be captured at the same rate as the external system clock

Signal Sets /Signals

I

8/16/32/64

Input channels. Signals are fed into the analyzer in grouped sets. Up to 16 signal sets may be defined, each containing n signal channels, where n is the defined Capture Width for the device. See Configuring the Signals to be Captured for more information.

Logic Analyzer Output Signals

STATUS

O

Level

This signal conveys the current state of the Logic Analyzer - whether it is capturing data or not.
0 = Not capturing data
1 = Currently capturing data

External Trigger Signals

EXT_TRIGGER

I

High

External trigger signal. Once the Logic Analyzer has been armed, a High level at this input will trigger the instrument and initiate capture of data. This signal allows for a hardware trigger to be defined, in addition to the software trigger defined from the instrument's associated LAX panel.

Memory Interface Signals (available when external LAX memory is used)

DATAO

O

8/16/32/64

Data bus output

DATAI

I

8/16/32/64

Data bus input

ADDR

O

20

Address bus output

WR

O

High

Memory write enable

RD

O

High

Memory read enable