Actel CoreMP7
Altium Designer's CoreMP7 component is a 32-bit Wishbone-compatible RISC processor, for use in FPGA designs targeting supported Actel Fusion or ProASIC®3 families of physical FPGA devices.
Altium Designer supports use of the CoreMP7 processor with the following Actel base FPGA devices:
Fusion – M7AFS600
ProASIC3 – M7A3P1000
Although placed in an Altium Designer-based FPGA project as a CoreMP7, this is essentially a Wishbone-compliant wrapper that allows use of Actel's corresponding 'soft' CoreMP7 processor core.
Similar to (and fully compatible with) the ARM7TDMI-S™ core processor, the CoreMP7 is an implementation of the ARM® architecture v4T. This RISC architecture supports both the 32-bit ARM instruction set, as well as the 16-bit Thumb instruction set. In addition, the CoreMP7 features a user-definable amount of zero-wait state block RAM, with true dual-port access.
Only designs targeting the supported Fusion or ProASIC3 FPGA devices may make use of the processor. Should you wish the freedom of both a device and FPGA Vendor-independent 32-bit system hardware platform, use the available TSK3000A 32-bit RISC processor.
Supply of these soft cores under the terms and conditions of the Altium End-User License Agreement does not convey nor imply any patent rights to the supplied technologies.
The Actel CoreMP7 soft processor core has no licensing fees or royalties associated with its use. However, in order to build the design for the target Actel FPGA device, you will need to install the relevant Vendor tools - Actel® Designeror Libero® IDEfrom www.actel.com. The software can be downloaded but does require a license. Check the website for licensing options.
Altium Designer supports versions 6.0 to 7.3 inclusive, of the Designer and LiberoIDE software.
Features at-a-glance
- Optimized for use in ARM-enabled Actel Fusion and ProASIC3 FPGA devices
- Compatible with ARM7TDMI-S processor
- Implementation of the ARM v4T RISC architecture.
- Supports 32-bit ARM instruction set
- Supports 16-bit Thumb instruction set
- 3-stage pipeline
- Internal von Neumann architecture
- Supports on-chip block RAM and/or external memory
- 4GByte address space
- Wishbone I/O and memory ports for simplified peripheral connection
- Full Viper-based software development tool chain - C compiler/assembler/source-level debugger/profiler
- C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant processor cores, for easy design migration.
Availability
From an OpenBus System document, the CoreMP7 processor can be found in the Processors region of the OpenBus Palette panel.
From a schematic document, the CoreMP7 processor can be found in the FPGA 32-Bit Processors integrated library (FPGA 32-Bit Processors.IntLib), located in the \Library\Fpga folder of the installation.
32-bit Processor FundamentalsDebuggingSee Also | Working with the CoreMP7For detailed information about the hardware and functionality of the CoreMP7, including internal registers, refer to the CoreMP7 Data Sheet (available from www.actel.com) and the ARM7TDMI-S Technical Reference Manual (available from www.arm.com). The ARM7TDMI-S core processor – on which the CoreMP7 is based – is an implementation of the ARM architecture v4T. For an overview of the ARM instructions available for this processor, refer to the ARM7TDMI-S Technical Reference Manual and ARM Instruction Set Quick Reference Card, available from the ARM website. For detailed information with respect to the ARM instruction set, including instruction encoding and an alphabetical listing of all instructions by mnemonic, refer to a printed publication such as the ARM Architecture Reference Manual. |