CoreMP7 Pin Description
Frozen Content
The pinout of the CoreMP7 has not been fixed to any specific device I/O – allowing flexibility with user application. The CoreMP7 contains only unidirectional pins (inputs or outputs).
The following pin description is for the processor when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces.
| Name | Type | Polarity/Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock |
| RST_I | I | High | External (system) reset |
| Interrupt Signals | |||
| INT_I | I | 32 | Interrupt inputs. Note: Only one interrupt line is used. The wrapper's least significant interrupt line (INT(0)) is internally connected to the CoreMP7's nIRQ input line, via an inverter. |
| Wishbone External Memory Interface Signals | |||
| ME_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| ME_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| ME_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes High, an external Wishbone slave memory device has finished execution of the requested action and the current bus cycle is terminated |
| ME_ADR_O | O | 32 | Standard Wishbone address bus, used to select an address in a connected Wishbone slave memory device for writing to/reading from |
| ME_DAT_I | I | 32 | Data received from an external Wishbone slave memory device |
| ME_DAT_O | O | 32 | Data to be sent to an external Wishbone slave memory device |
| ME_SEL_O | O | 4 | Select output, used to determine where data is placed on the ME_DAT_O line during a Write cycle and from where on the ME_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| ME_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read 1 = Write |
| ME_CLK_O | O | Rise | External (system) clock signal (identical to CLK_I), made available for connecting to the CLK_I input of a slave memory device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| ME_RST_O | O | High | Reset signal made available for connection to the RST_I input of a slave memory device. This signal goes High when an external reset is issued to the processor on its RST_I pin. When this signal goes Low, the reset cycle has completed and the processor is active again. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| Wishbone Peripheral I/O Interface Signals | |||
| IO_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| IO_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| IO_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes High, an external Wishbone slave peripheral device has finished execution of the requested action and the current bus cycle is terminated |
| IO_ADR_O | O | 24 | Standard Wishbone address bus, used to select an internal register of a connected Wishbone slave peripheral device for writing to/reading from |
| IO_DAT_I | I | 32 | Data received from an external Wishbone slave peripheral device |
| IO_DAT_O | O | 32 | Data to be sent to an external Wishbone slave peripheral device |
| IO_SEL_O | O | 4 | Select output, used to determine where data is placed on the IO_DAT_O line during a Write cycle and from where on the IO_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| IO_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read 1 = Write |
| IO_CLK_O | O | Rise | External (system) clock signal (identical to CLK_I), made available for connecting to the CLK_I input of a slave peripheral device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |
| IO_RST_O | O | High | Reset signal made available for connection to the RST_I input of a slave peripheral device. This signal goes High when an external reset is issued to the processor on its RST_I pin. When this signal goes Low, the reset cycle has completed and the processor is active again. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design |