Release Notes for the Summer 09 Service Pack 1 Release of Altium Designer

Summer 09 Service Pack 1 Build 9.1.0.18363 (from Build 9.0.0.17654)

PCB

• Significantly improved Libraries panel performance when browsing PCB libraries with a lot of STEP models.
• Fixed problem that prevented PCB documents being opened under Windows 2000 operating system.
• "Move Room" command will now work correctly when launched from "Room Actions" pop-up menu.
• PCBLib - FlipBoard command will now refresh the graphical view if in GDI graphics mode.
• List Index Out of Bounds error when clicking in the top side treeview of the Smart Grid Insert dialog is now fixed.
• Improved glossing quality when dragging tracks or vias. Glossing will be now less aggressive and restricted to objects being dragged. Added option to turn glossing off during these operations. More...
• Deleting Custom Layer Sets from a PCB has been made more reliable.
• Fixed crash when Full Stack via style was used in PCB Preferences >> Interactive Routing >> Favorite Interactive Routing Via Sizes.
• Escape Routing - Width rule that specifically refers to MidLayer tracks will be used instead of the default rule.
• The interactive route tool now uses the correct blind/buried via from the defined drill pairs. Previously, some layer stack configurations led to an incorrect via to be chosen.
• The IsRoundPad query will now return the correct result set when used. Added IsOctagonalPad query and also added new queries for getting the pads that have the desired PadShape on a specific layer. The new query functions are: IsRoundPadShapeOnLayer, IsSquarePadShapeOnLayer, IsRectangularPadShapeOnLayer, isOctagonalPadShapeOnLayer and IsRoundedRectangularPadShapeOnLayer.
• The "Connections and From Tos (Default Color)" was renamed to "Default Color for New Nets" because only the newly created nets will use this color. Updating this color will not change the color of any of the existing nets.
• When cycling backwards over layers in PCB editor a bug has been fixed where the mechanical layers were skipped.
• Fixed occasional crash in interactive router when swapping targets.
• The PCB List Panel Smart Grid Insert / Paste functions have been enhanced for Embedded Board objects. The user can now easily import and manipulate embedded board data including Location, Rotation and Spacing from spreadsheets and other table based sources.
• Fixed crash when the same Texture File was used on more than one extruded 3D body.
• Strings on plane layers in 3D will now display properly.
• Net antennas are now correctly removed with the Loop Removal tool.
• The Minimum Annular Ring DRC check will now give the correct result for boards containing pads with rotated slots and internal plane layers.
• Vias are now correctly teardropped using correct via size for layer instead of using largest via size found on any layer.
• Changed default column width in "Find Similar Objects" in PCB to better accommodate attribute descriptions.
• Fixed problem in differential pair router that was preventing vias having same size as the track width being placed.
• An issue with via plane connections has been fixed. The issue occurred in vias where the start layer was below the stop layer in the board stackup.
• The process of updating PCB Server Preferences has been improved. Now changing the status of Online DRC flag for example no longer enables all layers in the open PCB documents.
• The default sorting in the PCB panel has been changed so that it sorts Components by Designator and Nets by Net name.
• Fixed problem when minimum annular ring violations were not reported for some vias.
• Component Designator and Comment locked status will now be shown in PCB Inspector and PCB List panels.
• Fixed problem where following changes in layer stack manager were not applied: top/bottom dielectric attributes, net names on internal plane layers.
• Fixed rare ODB++ crash when invalid polygonal regions was passed to ODB++ generator.
• Fixed intermittent crash that was happening when track was dragged in HugnPush mode.
• Issue with signal layer tracks ignoring keepouts when dragged from non-signal layers has been fixed.
• The ODB++ output no longer generates an AV when the PCB document contains blind vias that have the Start and Stop layers reversed.
• Pads and vias in DirectX will now have more edge segments when zoomed in to improve display accuracy.
• Fixed bug where board cutouts have been treated as copper objects when "Select Connected Copper Ctrl+H" command was used.
• Fixed a couple of bugs in net analyzer code that were producing crashes in broken net DRC analysis as well in some cases of synchronization with schematic documents.
• File saving has been fixed for PCB documents that contain shelved polygons on Mechanical layers greater than 16. Previously such polygons were shifted to Mechanical Layer 16.
• The Pad, Via etc. Placement has been improved. Now an ambiguity pop-up containing nets will appear (if the number of found nets is greater then 1) from which the user will be able to select the Net to which the placed pad, via will be attached.
• The handling of shelved polygons has been improved so that a warning is given if a layer is deleted from the stack that contains shelved polygons.
• Fixed problem where interactive routers were unlocking previously locked objects.
• Special component strings having violations no longer cause AV when owner component is deleted from the board.
• Fixed access violation when DRC was run with "Report Broken Plane" option when no applicable and enabled unrouted nets rules were found.
• Tracks that are made co-linear after a drag command will now be merged into a single track.
• The behavior of dragging a track has been improved when the electrical grid is enabled. The cursor no longer snaps to the track being dragged.
• 3D bodies within rotated, flipped components will now follow the parent component's orientation correctly.
• Having the metric precision set lower than 5 could cause extremely long delays whenever a component clearance DRC was triggered. This has been fixed.
• The delay has been substantially reduced, when starting the Advanced Router in pin swapping mode.
• After toggling into accordion mode in Interactive Route, ~ or F1 now displays the proper hot keys shortcut menu.
• The criteria for determining testpoint pads and vias that constitute "leaf nodes" has been corrected, with respect to nodes that are connected to planes and copper pour polygons.
• The "Unrouted Net" violating primitives will no longer be drawn in violation color in GDI graphics mode.
• "Favorite Interactive Via Sizes" dialog will now show all layers when unchecking "Only Show Layers In Layer Stack" option.
• MaxMinWidth Rule will now work for all signal layers regardless of whether they are in the layer stack or not.
• Pad/Via FullStack "Pad Layer Editor" dialog now displays all layers if "Only show layers in layerstack" option is un-checked.
• "Select / Touching Line" command now correctly selects 3D bodies.
• PCB Library panel - Find Similar Objects - If "Whole Library" option is ON then the corresponding primitives in all library components will be selected not only those in the current component.
• Select Inside and Deselect Inside Area commands will now behave the same way when selecting or deselecting components.
• Show / Hide Tab in the View Configurations dialog - Toggle Shown pushbutton option now works as expected.
• Locked property of Designator / Comment will no longer be accessible in PCB Inspector and PCB List views. In PCB Inspector any ReadOnly properties will now be grayed out.

Schematic

• Fixed stack overflow crash when connecting arbiters in OpenBus document.
• SCHLIB component names whose 31st character is a space no longer cause STG errors. Files edited with S09 public release will need to be resaved.
• The Jump Component command now has a Physical checkbox which allows you to jump to a component by physical designator.
• The Sheet panel now refreshes correctly in physical document tabs.
• Tools >> Cross Probe from PCB to schematic no longer switches tabs to the compiled document unexpectedly.
• Sheet numbering in schematic prints no longer reverts to logical for the second and subsequent physical sheets of a multichannel project.
• Schematic documents can now be added to FPGA projects more reliably when using a Soft Design license and the Home Page is showing.
• There is now an =ProjectName special string in schematic that evaluates to the name of the project.
• Replace Text on Open Documents has been fixed.

FPGA

• MEM_CTRL component has been improved. 2x8 and 1x16 memory layout halfword wishbone transfer is correctly handled.
• Clock Manager components are now properly generated while targeting a Xilinx Virtex-5 device.
• Hex files containing data larger than 64kB are now correctly written to Parallel Flash on NB2 and NB3000 via the TSK3000 instrument.
• The WB_SPI, WB_SPI8 and WB_SPI32 cores have been improved and no longer include latches.
• Pull Up and Pull down constraints in the Constraints editor are now properly set and pass to Lattice ispLEVER and Actel Designer.
• The Xilinx PPC405A processors available for some Virtex-2Pro and Virtex-5 devices are now automatically placed at the beginning of the JTAG soft chain to avoid problems.
• It is now possible to set the Nanoboard clock frequency from within a script file.
• Altera Nios II version 8.0 is now properly detected in the Devices View.
• Support for the NanoBoard 3000AL has been added.
• Actel Libero 8.6 is now properly found in the Devices View.
• Synplify 2009 no longer generates an internal error at start up.
• The Map Design stage of the FPGA flow no longer fails with an error "Invalid Package pin at PDC Line" for pins starting with "P" while targeting an Actel device with a FCS package.
• Using a Custom Wishbone Interface schematic component with its default settings is no longer causing the Synthesis stage of the FPGA flow to fail with an error "adr_i is not declared".
• Re-connecting a script project to a NanoBoard Interface component in the Structure Editor of the Projects panel is now properly updating the Configuration string of the corresponding NanoBoard Instrument component in the Schematic editor.
• A typo has been corrected in the Configure dialog of the NanoBoard Instrument dialog.
• The Polling function of the Devices View is no longer causing the Memory Instrument / Probes panels to get focused automatically when they are currently opened.
• The USB_INTERCON component is no longer causing the Place and Route stage of the FPGA flow in the devices view when targeting a device other then a Xilinx Spartan-3AN.
• Refreshing the Devices View will re-compile FPGA projects only if changes have been made since the last compile.
• Setting the optimization technique option of the FPGA flow to "speed" while targeting an Altera Cyclone-3 device is no longer causing an error "Illegal assignment: CYCLONEIII_OPTIMIZATION_TECHNIQUE".
• FPGA projects no longer re-opened when the Devices View is automatically refreshed via the Polling function and the Close Project command has been invoked at the same time.
• The Configure dialog for configurable counter components is no longer defaulting the signal width field to 1 when invoked.
• The Xilinx Spartan-3A FPGA integrated library has been reviewed and is now including a symbol for the SPI_ACCESS primitive.
• Selecting the Logic Analyzer >> Run Logic Analyzer or Start Continuous Capture commands in the Digital LAX editor is no longer causing a crash to occur when the Live option in the Devices View has been unchecked.
• Synthesizing core projects while using the Xilinx XST synthesizer is no longer causing an error "Xst:426 Illegal command usage : run" to occur.
• The responsiveness of the LAX Instrument Panel has been improved when setting the LAX trigger options.
• Script with endless recursion no longer causes Altium Designer to terminate without warning.
• Importing constraints from Lattice *.pad files into the Constraints editor is now removing the '_' suffix from the bus names.
• A memory leak while using button control in instrument panels has been resolved.
• Crash is fixed in Altium Designer when going live in Devices View, after Dashboard releases JTAG.
• Fixed JTAG-SPI flash write failing. Fixed incorrect reading of USB descriptor strings on AMD based hardware. Enhanced error handling ability of JTAG communication.
• The Synthesis stage of the FPGA flow no longer failed with an error "Unable to find Synplicity for Actel" while targeting an Actel device and using the Synplify for Actel synthesizer.
• It is now possible to set default document template for OpenBus documents.
• The Configure JTAG ID Mapping dialog for configuring Generic JTAG devices has been reviewed and is no longer displaying superfluous controls.
• The Configurable Clock Manager component no longer fails to synthesize with an error "type real does not match with the integer literal" when the Windows regional and settings is set to a European language like French or German.
• The Make STAPL File stage of the FPGA flow no longer fails with an error "Input file is not a STAPL file" when running the second time while targeting an Actel device.
• The OpenBus dual port connector is no longer generating errors when synchronized using signal harnesses.
• The signals of the dipswitches in the NB3000XN constraints file are no longer in reversed order.
• Fast slew rate constraints have been added to the Shared Memory Bus signals in the NB3000XN constraints file for the SDRAM to operate reliably.
• The SPDIF_OUT pin designator of the SPDIF component of the FPGA NB3000XN Port Plug-In library has been renamed to match the corresponding constraints files.
• A C file is now automatically created if a non-existing C file is set in the properties dialog for C Code Symbols instead of being unable to save the changes before exiting the GUI.
• The FPGA Third Party Import Wizard is now properly importing cores that have been generated in NCO format while targeting Lattice devices.
• Programming an FPGA with a NanoBoard Interface instrument that will reset the device from its script no longer causes the system to crash.
• Multiple fixes for WB_PROBE instrument.
• Support for Actel IGLOO devices have been added.
• A crash no longer occurs in the HDL compiler and the Altium Synthesizer when an HDL file contains a declaration of a large uninitialized array.
• The DAT_I port of the ASP component is now properly generated when only ROMs are attached to its memory bus.
• Enabling the Init Memory option of a C Code Symbol with a Combinatorial function is no longer causing the errors "formal clock has no actual or default value" and "formal reset has no actual or default value" to occur.
• The Custom Wishbone Interface configurable component now has an extra option "Number of channels" to create multiple instances of the same interface.
• Support for Actel IGLOO E devices have been added.
• Support for Actel IGLOO Plus devices have been added.
• Support for Actel IGLOO nano devices have been added.
• Automatic firmware updater is now available for the NanoBoard 3000 series. When a new firmware version is available, Altium Designer will initiate the firmware update process if a NanoBoard 3000 is detected. More...

System-level

• Fixed accidental crash in code editor.
• Fixed accidental lock up in script editor after stopping script with an error.
• Fixed: The code explorer doesn't show the name of the procedure or function for Delphi Script.
• Fixed Call stack panel for script languages.
• There is now an option in Preferences>>System>>Account Management to disable all connection to your Altium account. More...
• The Comparator tab in project options now lets you choose whether to detect Different Comments, Designators, Descriptions, Footprints, and Libraries case sensitively or case insensitively. This affects the Show Differences, Update PCB, and Update Schematic commands.
• A crash associated with long strings of non-English characters in edit controls (for example, on the schematic Component Properties dialog) has been fixed.
• Component variations are no longer applied to incorrect components after schematics are reannotated. But if a component's UniqueID changes (for example, by being deleted and replaced with the same physical designator), then any existing variant information will no longer apply to it automatically. You must now either run the Assembly Variants dialog again and click OK to relink any existing variant information to it, or reapply the variant information manually.
• The P-CAD importer now imports vertical ports with orientation of 270 degrees and the flipped checkbox on correctly.
• The P-CAD importer should now position power ports correctly and associate them with the right nets.
• The P-CAD importer now imports part Types as Comments.
• The Output Media in an OUTJOB document can now be reordered, by dragging and dropping.
• Dragging a file into the central frame of the Home page no longer opens that file in the frame.
• The Assembly Variants toolbar no longer disappears if you import preferences from releases of Altium Designer earlier than Summer 09.
• Parameters of an Assembly Variant are now available in the Bill of Materials (overriding any Project parameters of the same name) by including Field=parameter name in the template.
• Searching the Wiki via the Knowledge Center panel for words containing non-English characters now works correctly.
• A rare crash in IntegratedLibrary.DLL related to downloading exchange rates from the Altium Account Management server has been fixed.

Embedded

• The TSK3000 linker no longer issues an error message when an ASP component is used together with software platform multi-threading support.
• The information in the Call Stack debugging window for multi-threaded applications has been improved.
• The local option "Show program builder dialog" for embedded projects was moved to the global DXP Preferences.
• The debugger is able to step over inlined function calls unless these calls are too much affected by compiler optimizations.
• The embedded project's local "Save before compile" option has been removed. This option is also available globally under DXP Preferences for Embedded System.
• The number of situations which lead to the occurrence of the debugger's "no storage assigned" message when evaluating local variables has been reduced.
• MicroBlaze C library now contains the global __clocks_per_sec which is used by parts of the SoftwarePlatform.
• The linker no longer reports multiple defined symbols when the application includes more than one of the driver plugins for UART, IRRC, or IR38K.
• Fixed bug with opening empty Schematic sheet after changing options in Software Platform document.
• Software Platform no longer affected by decimal symbol settings (Regional options) in Windows.
• Erasing the parallel flash from the "Write To Flash ..." menu now erases all sectors, not only the first one.

CAM Editor

• Now the NCDrill Import will be rolled back if the Cancel button is pressed in the "Import Drill Data" dialog.

Signal Integrity and Simulation

• Parametric import into SimView using the ImportWaveforms command has been improved. Complex status of waves is now correctly set, waves are overwritten properly for complex waveforms, a ChartType parameter has been added and some new parameters added to control X scale attributes.

Library Management

• Farnell and Newark Customer ID support has been removed pending server side changes to be made by Premier Farnell.