Search
Search results
-
Domain User Vault Access
... Directory http://docs.ubersvn.com/v1.0/ac.html#310 Lightweight Directory Access Protocol ...
phil.loughhead@... - 05/31/2017 - 18:39
-
Viewing Data Captured by the Logic Analyzer
... instruction length is 32-bits. The captured signal DATA 31..0 is 32 bits wide and so is disassembled. Should you wish to hide ...
admin - 09/13/2017 - 15:32
-
Domain User Vault Access
... Directory http://docs.ubersvn.com/v1.0/ac.html#310 Lightweight Directory Access Protocol ...
admin - 09/13/2017 - 15:32
-
Tutorial - Checking Signal Integrity on an FPGA Design
... to answer the question "How hard can I drive the signals D[31..0] before ringing and crosstalk will prevent correct operation?" Or ... and drive settings to use for FPGA pins driving signals D[31..0]?" This tutorial relates to the example project Nbp-28.PrjPcb , ...
admin - 11/12/2013 - 03:12
-
Tutorial - Checking Signal Integrity on an FPGA Design
... to answer the question "How hard can I drive the signals D[31..0] before ringing and crosstalk will prevent correct operation?" Or ... and drive settings to use for FPGA pins driving signals D[31..0]?" This tutorial relates to the example project Nbp-28.PrjPcb , ...
admin - 09/13/2017 - 15:32
-
C Code Symbol
... additional STB_I, CYC_I, ACK_O, ADR_I[17..0], DAT_O[31..0], DAT_I[31..0], SEL_I[3..0], WE_I, CLK_I, RST_I with prefix FunctionName_ C Code ... mode is selected, additional STB_I, CYC_I, ACK_O, DAT_O[31..0], DAT_I[31..0], SEL_I[3..0], WE_I, CLK_I, RST_I C Code Entries will ...
admin - 11/19/2013 - 09:15
-
WB_SDCARD - Accessible Internal Registers
... in which case: For transmission DAT_I(31..0) is loaded into TX_DATA(31..0) For reception RX_DATA(31..0) is presented on DAT_O(31..0) Otherwise, if '0', a Little Endian ...
admin - 11/06/2013 - 09:09
-
WB_SDCARD - Accessible Internal Registers
... in which case: For transmission DAT_I(31..0) is loaded into TX_DATA(31..0) For reception RX_DATA(31..0) is presented on DAT_O(31..0) Otherwise, if '0', a Little Endian ...
admin - 09/13/2017 - 15:32
-
WB_SPI - Accessible Internal Registers
... in which case: For transmission DAT_I(31..0) is loaded into TX_DATA(31..0) For reception RX_DATA(31..0) is presented on DAT_O(31..0) Otherwise, if '0', a Little Endian ...
admin - 09/13/2017 - 15:32
-
WB_SPI - Accessible Internal Registers
... in which case: For transmission DAT_I(31..0) is loaded into TX_DATA(31..0) For reception RX_DATA(31..0) is presented on DAT_O(31..0) Otherwise, if '0', a Little Endian ...
admin - 11/06/2013 - 09:09